Ultra-low-power CMOS ring oscillator with minimum power consumption of 2.9 pW using low-voltage biasing technique

Durgham Al-Shebanee

doi:10.1515/eng-2022-0448

Article Open Access

Ultra-low-power CMOS ring oscillator with minimum power consumption of 2.9 pW using low-voltage biasing technique

Durgham Al-Shebanee

Published/Copyright: February 22, 2024

Published by

Become an author with De Gruyter Brill

Submit Manuscript Author Information

From the journal Open Engineering Volume 14 Issue 1

Abstract

The need for low-power low-voltage circuit so lutions increases significantly with the rapid spread of wireless sensor network (WSN) and energy harvesting applications. The design of Complementary Metal-Oxide Semiconductor (CMOS) oscillators in sub-threshold region is challenged by the limits of the minimum start-up sup ply voltage, the power available from the harvester, die area, the demand of fully integrated CMOS circuits, and the additional auxiliary circuits that are needed to stabilize the frequency vs a supply voltage V _DD. In this work, low-power CMOS oscillator with a simplified design is proposed in order to overcome the aforementioned obstacles. The circuit is designed using 2.5 µm 2-polySi 2-metal CMOS technology from IMB–CNM (CSIC) [1] with a threshold voltage of n-channel metal oxide semiconductor NMOS and p-channel metal oxide semiconductor PMOS transistors of 0.86 and −1.52 V, respectively. The suggested oscillator is capable to start up even in the deep sub-threshold region at V _DD of 0.25 V. Accordingly, the minimum power consumption is 2.9 pW with an oscillation frequency of 2 Hz. The circuit can produce a P–P voltage of the oscillation signal equal to the supply voltage within a power supply range of 0.25–1.25 V.

Keywords: low-power CMOS circuits; low frequency oscillator

1 Introduction

Oscillators are an essential part of various electronic circuits like clock generators, timers, audio and video sys tems, radio frequency (RF) systems, and power management applications. In energy harvesting applications, the voltage produced by the transducer is extremely low. Thus, DC to DC (DCDC) voltage converter is needed to reach an accepted output DC voltage that is sufficient for a conventional electronic circuit. DCDC converters use oscillators to drive the switches of the charge pumps or inductor-based voltage converter. Consequently, as the oscillator can start up with low voltage, the harvested power can be usable even in challenging conditions such as low light intensity for solar cells or a far distance between the receiver and transmitter in RF energy harvesting. Low frequency timers, on the other hand, are necessary circuits in WSNs and Internet of Things (IOT) applications. The oscillator type and design can be determined according to the supply voltage. The minimum V _DD needed to start- up the inductor-capacitor (LC)-based oscillator is lower than that needed for the ring oscillator. The low-voltage oscillator proposed by Radin et al. [2] is based on using four off-chip inductors as shown in Figure 1. The high ratio of L2/L1 reduces the minimum supply voltage required to start-up the oscillator and increases the amplitude of the generated signal. The oscillator starts up at 7.3 mV. Unlike off-chip inductors, on-chip inductors can be used in various applications like RF applications [3] and low voltage oscillators. An on-chip inductor has been used in low- voltage oscillator [4]. An oscillation signal of 1 GHz has been generated with a minimum supply voltage of 200 mV. In addition to the required large die area, the high frequency signal can cause high losses. Moreover, various solutions have been given by CMOS technology in low-power circuits like DCDC converters [5]. Ring oscillators give a competitive choice in opposition to the lossy on-chip inductor or the undesired off-chip inductor. The conventional oscillator can be simply built by several inverters as shown in Figure 2. However, operating the ring oscillator with low supply voltage is challenged by the need for high open loop gain [6]. Consequently, a large number of inverter stages is needed while every stage is built by extra wide transistors that consume undesirable high power. For low supply voltage applications, NMOS and PMOS transistors are biased in sub-threshold region. The drain–source current I _d is expressed as follows [7]:

(1) I ds = μ n C ox ϕ t 2 W n L n 1 − k n k n e k n V g − V s − V th ϕ t ,

where µ _n is the carrier mobility, C _ox is the gate oxide capacitance, φ _t is the thermal voltage, W _n and L _n are the width and length of the transistor, respectively, k _n is the capacitive-divider ratio, V _th is the threshold voltage, V _g is the gate voltage, and V _s is the source voltage. Equation (1) shows clearly how V _gs and V _th have a dominant effect on the current and the gain. As high gain is obtained, a low supply voltage is capable to start up the oscillation. As mentioned above, it is possible to increase the open loop gain by using a large number of stages accompanied with high -power budget. Various topologies have been given to lower the minimum V _DD limit of ring oscillators [8,9,10,11]. A low-voltage oscillator based on a 3-stage redundant inverter composed of 7 stages is presented by Luo et al. [12] (Figure 3). The oscillator starts up at 45 mV. Nevertheless, the oscillator requires large number of inverters that consume additional power. For low-frequency timers, numerous designs have been given in the literature. A current-starved inverter based oscillator has been used in Kalburgi et al. [13] with oscillation frequency of 32.768 kHz. The frequency has been stabilized with temperature using a temperature independent current source. However, the supply voltage range is narrow while the minimum needed V _DD and power consumption are high. Another design of low-power relaxation oscillator based on Wheatstone bridge scheme has been given by Chen et al. [14] with frequency of 16.5 kHz. The power consumption is relatively high. An alternative topology for the conventional inverters has been presented by Ponce et al. [15] with frequency of 0.0308 Hz. This circuit uses CMOS thyristors as delay elements in a ring oscillator with a small number of inverters so that the area and the power consumption are reduced. The minimum needed supply voltage is high for low-power applications. An oscillation signal with a frequency of 1.82 Hz has been generated by Barbruni et al. [16] to be used in medical applications. This circuit based on a voltage controlled oscillator that uses down-scaling technique of the transistor. The power consumption is undesirably high. A low frequency relaxation oscillator in neuromorphic applications has been given by Cheng et al. [17]. The circuit adopts 250 pA charging current for low oscillation frequency. A reconfigurable frequency from 3.15 to 81.3 Hz has been obtained while the supply voltage is high. Another topology for charging a capacitor using a differential leakage technique has been presented by Nishio et al. [18]. The frequency of the generated signal is 0.11 Hz while the minimum power consumption is 4.5 pW. The supply voltage range is narrow and it strongly influences the oscillation frequency. A timer with a wider supply voltage range and less line sensitivity has been reported by Kobayashi and Niitsu [19]. The timer is based on the gate leakage technique without using an amplifier. However, the power consumption is relatively high concerning the ultra-low-power applications.

Figure 1

Off-chip inductor-based oscillator with minimum V _DD of 7.3 mV [2].

Figure 2

Conventional ring oscillator with push–pull inverter used as a construction unit.

Figure 3

3-stage redundant inverter used in low 7-stage voltage oscillator [12].

The main aim of this work is to present a design that avoids off-chip solutions like inductors. Moreover, the on-chip inductors and capacitors are also avoided in this work in order to reduce the die area. This work presents an alternative solution of using frequency divider stages, or delay stages that are used to lower the oscillation frequency. Minimum supply voltage limit is the prior criteria in this design. Therefore, the circuit design aims to operate the circuit in sub-threshold region. A wide supply voltage range is preferable in order to keep the oscillator performance stable with V _DD variations.

In this work, ultra-low-power oscillator is presented with a simplified methodology that lowers the minimum V _DD required to start-up the oscillation. Instead of the conventional inverter topologies, the suggested circuit is based on modified inverter stages that are capable to work in the deep sub-threshold region. Moreover, a reference voltage circuit is used to stabilize the frequency of the generated signal and the drawn current when the supply voltage increases. The rest of this work is presented as follows: Section 2 explains the proposed methodology for a low-power low-voltage oscillator including the circuit topology. Section 3 lists the main design parameters and demonstrates the simulation results with analysis. Section 4 summarizes the conclusion of this work.

2 Circuit structure and operation concept

As explained in Section 1, the push–pull inverters represent the ordinary construction unit of ring oscillators. Alternatively, a common source inverter stage is suggested as shown in Figure 4. The transistor Mosc2 is used as a current source that is biased in the deep sub-threshold region as it is expected that the supply voltage is less than V _th. In ordinary circuit topology, it is expected that the drawn current increases exponentially with the power supply. Consequently, the clock frequency increases so that the power losses is maximized. On the other side, biasing the oscillator with a constant current is necessary to guarantee a constant frequency and stable power consumption with the supply voltage. According to the given topology, with proper sizing of the used devices, the Peak-to-Peak P–P voltage of the oscillation signal can be equal to V _DD for a wide range of power supply variations. A supply independent voltage reference circuit has been used to produce the signal V _ref as shown in Figure 4. The biasing circuit is based on the conventional technique that has been given previously in literature for the cancellation of the threshold voltage temperature coefficients of the NMOS transistors. However, in this topology, standard NMOS transistors have been used while the reference voltage is proportionally related to temperature because the transistor Mb1 is wider than Mb2. The signal V _ref is applied to the gate terminal of Mosc2 to guarantee a constant drain current even when the power supply is changed. Consequently, the frequency is stabilized with supply voltage.

Figure 4

Ultra-low-power CMOS ring oscillator using common source inverter stage and reference voltage circuit.

3 Design and simulation results

The proposed oscillator has been designed using 2.5 µm 2-polySi 2-metal CMOS technology from IMB–CNM (CSIC) [20] while the circuit has been built using Glade (Gds, Lef and Def Editor) as an IC layout and schematic editor [21]. Standard NMOS and PMOS transistors have been used without low V _th or native devices. The oscillator consists of 11 stages. The sizes of PMOS transistors have been maximized because of the high threshold voltage. In order to increase V _ref, the aspect ratio of Mb1 has been enlarged to be much higher than that of Mb2. Table 1 shows the aspect ratios of the transistors used in the circuit. The operation conditions of the circuit match with the expected practical conditions of sharp variations in supply voltage as well as ultra-low-power available from the source. The circuit simulation has been performed using SPICE engine for Optimization Utilities SPICE OPUS [22]. The reference voltage has been defined to be 0.2 V and it is kept stable against the supply voltage variation as shown in Figure 5. The simulation results show that the minimum supply voltage required to start up the oscillation is 0.25 V with a signal frequency of 2.04 Hz. This is well below the threshold voltages of the used transistors so that the oscillator can start-up in deep sub-threshold region. The drawn current at minimum supply voltage is 11.5 pA as shown in Figure 6. The biasing signal V _ref keeps the drawn current in minimum possible range when the supply voltage increases. Consequently, the frequency has been relatively stabilized with V _DD as shown in Figure 7. The circuit is capable to generate an undistorted signal with P–P voltage equal to V _DD within the same supply voltage range as demonstrated in Figures 8 and 9. The simulation results show that the minimum V _DD, the range of V _SS variations, and power consumption are comparable to the previously published literature as shown in Table 2.

Table 1

Sizes of transistors

Transistor name	W L
Mosc1	15 3 μm 3 μm
Mosc2	3 μm 4 μm
Mb1	40 μm 3 μm
Mb2	3 μm 3 μm

Figure 5

Variation in the biasing signal V _ref with the supply voltage.

Figure 6

Variation in the total drawn current with the supply voltage.

Figure 7

Variation in the oscillation frequency with the supply voltage.

Figure 8

The output signal V _osc with a supply voltage of 0.25 V.

Figure 9

The output signal V _osc with a supply voltage of 1.25 V.

Table 2

Performance comparison

	This work	[15]	[16]	[17]	[18]	[19]	[13]	[14]
Technology	2.5 µm	350 nm	180 nm	130 nm	130 nm	55 nm	180 nm	180 nm
Frequency (Hz)	2	0.0308	1.82	3.15–81.3	0.11	322	32,768	16,500
Supply Voltage (V)	0.25–1.25	3.3	1.8	3.3	0.29	0.35	1.7–1.9	1.2–1.9
Min. power	2.9 pW	1.98 nW	1.82 nW	24 nW	4.5 pW	22 nW	250 nW	22 nW

4 Conclusion

Ultra-low-power CMOS ring oscillator has been presented. The circuit can perform with minimum power consumption of 2.9 pW giving low-power solution for various applications that have low-frequency-driven circuits. Moreover, low-voltage biasing technique has been suggested in order to stabilize the current and frequency with supply voltage. The simulation results show that the oscillation frequency changes with 30% for the power supply range of 0.25–1.25 V. The oscillator starts up with minimum V _DD of 0.25 V. As mentioned before, the threshold voltages of NMOS and PMOS transistors used in this design are 0.86 and −1.52 V, respectively. This guarantees that the minimum V _DD limit required for oscillation can be lowered with another standard CMOS technology of less threshold voltage.

Acknowledgment

I would like to express my gratitude to the Ministry of Higher Education and Scientific Research in Iraq for granting me a sabbatical at RWTH Aachen University in Germany, as well as my thanks for the funding and support in this research in addition to the attribution and follow-up during the sabbatical duration. I would like to express my appreciation and thanks to the chair of Integrated Analog Circuits and RF Systems at RWTH Aachen University in Germany for hosting me and providing providing all that is necessary for the success of the research activity during the sabbatical duration.

Funding information: The funding of this research including the scientific sabbatical at RWTH Aachen University in Germany was by the Ministry of Higher Education and Scientific Research in Iraq and RWTH Aachen University in Germany.
Conflict of interest: The author states no conflict of interest.
Data availability statement: Most datasets generated and analyzed in this study are in this submitted manuscript. The other datasets are avail-able on reasonable request from the corresponding author with the attached information.

References

[1] Pallarès J, Sabine K, Terés L, Serra-Graells F. An academic EDA suite for the full-custom design of mixed-mode integrated circuits. In 2017 IEEE International Symposium on Circuits And Systems (IS-CAS); 2017. p. 1–4.Search in Google Scholar

[2] Radin RL, Sawan M, Galup-Montoro C, Schneider MC. A 7.5 mV-input boost converter for thermal energy harvesting with 11 mV self-startup. IEEE Trans Circuits Syst II: Express Briefs. 2019;67(8):1379–83.Search in Google Scholar

[3] Roy A, Harun Rashid A. Optimization of building blocks for multi-stage 17–44 dB 6.1–9.6 mW 90-nm K-band front-ends. Cent Eur J Eng. 2013;3:644–59.Search in Google Scholar

[4] Pathirana W, Jayaweera H, Muhtaroglu A. Low input voltage and high step-up integrated regulator for thermoelectric energy harvesting. In 5th International Conference on Energy Aware Computing Systems and Applications; 2015. p. 1–4.Search in Google Scholar

[5] Chander S, Agarwal PandGupta I. ASIC and FPGA based DPWM architectures for single-phase and single-output DC-DC converter: A review. Open Eng. 2013;3(4):620–43.Search in Google Scholar

[6] Razavi B. Design of analog CMOS integrated circuits. New York: Tata McGraw-Hill Education; 2002.Search in Google Scholar

[7] Harpeshkar R. Ultra low power bioelectron-ICS: Fundamentals, biomedical applications, and bio-inspired system. Cambridge: Cambridge University Press; 2010.Search in Google Scholar

[8] Bose S, Anand T, Johnston ML. Integrated cold start of a boost converter at 57 mV using cross- coupled complementary charge pumps and ultra-low-voltage ring oscillator. IEEE J Solid-State circuits. 2019;54(10):2867–78.Search in Google Scholar

[9] Dezyani M, Ghafoorifard H, Sheikhaei SandSerdijn WA. A 60 mV input voltage, process tolerant start-up system for thermoelectric energy harvesting. IEEE Trans Circuits Syst I: Regul Papers. 2018;65(10):3568–77.Search in Google Scholar

[10] Bose S, Johnston ML. A stacked-inverter ring oscillator for 50 mV fully-integrated cold-start of energy harvesters. In 2018 IEEE International Symposium on Circuits and Systems (ISCAS); 2018. p. 1–5.Search in Google Scholar

[11] Nishi M, Matsumoto K, Kuroki N, Numa M, Sebe H, Matsuzuka R, et al. A 34-mV startup ring oscillator using stacked body bias inverters for extremely low-voltage thermoelectric energy harvesting. In 2020 18th IEEE International New Circuits and Systems Conference (NEWCAS); 2020. p. 38–41.Search in Google Scholar

[12] Luo Z, Zeng L, Lau B, Lian YandHeng C-H. A sub-10 mV power converter with fully integrated self-start, MPPT, and ZCS control for thermoelectric energy harvesting. IEEE Trans Circuits Syst I: Regul Pap. 2017;65(5):1744–57.Search in Google Scholar

[13] Kalburgi S, Gupta D, Holi S, Shetty R, Annigeri S, Shraddha H, et al. Ultra low power low frequency on-chip oscillator for elapsed time counter. In 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID); 2019. p. 251–6.Search in Google Scholar

[14] Chen P, Li D, Yu Z, Jin Q, Yang K. A 0.84 pJ/cycle wheatstone bridge based CMOS RC oscillator with reconfigurable frequencies. In 2019 IEEE Custom Integrated Circuits Conference (CICC); 2019. p. 1–4.Search in Google Scholar

[15] Ponce PM, Sayed G, Saleh LA, Krautschneider WH, Kuhl M. A 1.9 nW timer and clock generation unit for low data-rate implantable medical devices. In 2020 IEEE 11th Latin American Symposium on Circuits and Systems (LASCAS); 2020. p. 1–4.Search in Google Scholar

[16] Barbruni GL, Bielli C, Demarchi D, Carrara S. Transistor downscaling toward ultra-low- power, sub-100 mum2 and sub-Hz oscillators. In SMACD/PRIME 2021; International Conference on SMACD and 16th Conference on PRIME; 2021. p. 1–4.Search in Google Scholar

[17] Cheng X, Birkoben T, Kohlstedt H, Bahr A. A CMOS integrated low-power, ultra-low- frequency relaxation oscillator for neuromorphic applications. In 2021 IEEE International Mid- west Symposium on Circuits and Systems (MWS- CAS); 2021. p. 170–4. 10.1109/MWSCAS47672.2021.9531896.Search in Google Scholar

[18] Nishio Y, Kobayashi A, Niitsu K. A 28 µm2, 0.11 Hz, 4.5 pW gate leakage timer using differential leakage technique in 55nm DDC CMOS for small-footprint, low-frequency and low-power timing generation. In 2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS); 2017. p. 368–71. 10.1109/ICECS.2017.8292063.Search in Google Scholar

[19] Kobayashi A, Niitsu K. Low-voltage gate-leakage-based timer using an amplifier-less replica-bias switching technique in 55-nm DDC CMOS. IEEE Open J Circuits Syst. 2020;1:107–14. 10.1109/OJ-CAS.2020.3007393.Search in Google Scholar

[20] Graells FS. Academic process design kit CNM25 edition. Academic process design kit (APDK) [online], 2023. www.cnm.es/users/pserra/apdk.Search in Google Scholar

[23] Klemetti A, Räsänen E. Foundations and case studies on the scalable intelligence in AIoT domains. Open Eng. 2022;12(1):878–89.Search in Google Scholar

Received: 2023-02-15

Revised: 2023-04-11

Accepted: 2023-04-23

Published Online: 2024-02-22

This work is licensed under the Creative Commons Attribution 4.0 International License.

Articles in the same Issue

https://doi.org/10.1515/eng-2022-0448

Keywords for this article

low-power CMOS circuits; low frequency oscillator

Creative Commons

BY 4.0