Large-scale silicon photonics switches for AI/ML interconnections based on a 300-mm CMOS pilot line

2.1.1 Fabrication, packaging, and control

The 32 × 32 switch adopts the PILOSS topology, utilizing double Mach–Zehnder (MZ) switch elements [28], [30] to improve crosstalk and its operating bandwidth. The configuration of the double-MZ switch element, and a 4 × 4 example of a PILOSS switch matrix employing this switch element, is depicted in Figure 1(a) and (b), where each double-MZ switch is designed to operate in the normally cross state.

Figure 1:

Path-independent insertion loss topology based on double-MZ switch element. (a) Configuration of double Mach-Zehnder (MZ) switch element. (b) Example for a 4 × 4 port configuration. The red, orange, green, and blue lines indicate path 1-–1′, 2–2′, 3–3′, and 4–4′, respectively.

In Figure 1(a), when the double-MZ switch is in the cross state, both individual MZ switches operate in the bar state. In this configuration, input port 1 is connected to output port 2′, and input port 2 is connected to output port 1′. Since port 2′ is connected to the output port of the switch matrix, leakage light from port 2 to port 2′ contributes to the overall crosstalk. This leakage is attenuated twice by the MZ switches in the bar state within the double MZ switch structure, which effectively suppresses crosstalk.

On the other hand, when the double-MZ switch is in the bar state, both MZ switches are in the cross state. Light from port 2 is directed to port 2′. Light from port 1 is routed to the idle port of the rear MZ switch. However, this route is unused. No light is inputted into port 1 when the double MZ switch is in the bar state. This is because, in the PILOSS configuration, the paths do not intersect at the bar state switch.

When constructing the PILOSS topology using the double-MZ switch, the switches are arranged with alternating orientations in both the row and column directions, as illustrated in Figure 1(b). In this configuration, the overall crosstalk of the switch matrix is primarily determined by the intersections. We have developed and employed an optimized adiabatic intersection structure that achieves excellent performance [29].

We designed the 32 × 32 switch for the TE mode and fabricated it by using our 300-mm silicon-photonics pilot-line described before. Figure 2(a) shows the fabricated switch chip with a chip size of 11 mm × 25 mm. The switch matrix consists of 1,024 double-MZ switch elements (i.e., 2,048 MZ switches) and 1,985 intersections. Edge couplers for input and output are placed at both ends of the chip. Figure 2(b) shows a micrograph of double-MZ switch element. Directional couplers were employed as the 3 dB couplers in each MZ switch, whose insertion loss is much lower than that of multimode interference couplers. The thermo-optic (TO) phase shifters based on TiN heaters have a time constant of approximately 30 μs, which can be reduced to a few microseconds using the turbo-pulse technique [31], [32].

Figure 2:

Microscope image of fabricated switch. (a) Chip. (b) Enlarged image of fabricated double Mach-Zehnder switch element.

For electrical packaging, we employed a flip-chip bonding technique. The chip contains 2,114 electrode pads for controlling and grounding the 2,048 MZ switches, which need to be fanned out and connected to the control board. The switch chip was flip-chip bonded to a ceramic interposer with 0.5-mm pitched land-grid-array (LGA). After attaching optical fiber arrays to the switch chip, the interposer was inserted into a 2,114-pin socket mounted on the control printed circuit board (PCB). The control PCB incorporates five field programmable gate arrays (FPGAs), enabling individual control of all MZ switches on the chip. These FPGAs generate electrical pulses at a repetition rate of 1 MHz, and the power delivered to each MZ switch heater is adjusted by tuning the duty cycle of the pulses. The total power consumption when all input ports are connected to their designated output ports was estimated to be 27.3 W. Of this, 26.0 W was used for calibrating the initial phase errors of the MZ switches, and 1.3 W was required to switching. In the fabricated 32 × 32 switch, only one arm of each MZ switch was electrically wired due to a limitation in the number of interposer electrodes. As a result, roughly half of the MZ switches required phase shifts exceeding 2π for phase trimming, leading to increased power consumption. If both arms of the MZ switches could be controlled, the total power consumption is expected to be reduced to approximately 10 W. Note that our fabricated MZ switch elements have nearly equal arm lengths, making them insensitive to ambient temperature fluctuations that almost equally change the temperature of both the arms. Therefore, no temperature control or cooling is required.

In the fabricated 32 × 32 switch, 16 out of the 2,048 MZ switches failed to operate as described in the next subsection. This issue is attributed to the disconnections at the flip-chip bonding and the contact failures between the interposer and the socket. Therefore, improvements in the parts and processes are necessary. Controlling both arms of each MZ switch by doubling the number of electrodes to ensure redundancy is also under consideration. Although this would require approximately 4,000 electrodes, recent semiconductor packaging technologies have exhibited the capability to handle up to 4,938 electrodes [33], making this approach a feasible option. Other potential solutions include reducing the number of control electrodes via time-division control [34] or monolithically integrating the control electronics.

For optical packaging, two 38-port optical fiber arrays were bonded to the edge coupler arrays at both edges of the chip. High numerical aperture fibers with a mode field diameter (MFD) of 4.0 μm at a wavelength of 1.31 µm were used in the fiber array. The fiber array was actively aligned to minimize coupling loss at both ends of the chip and subsequently fixed in place using UV-curable adhesive.

Even when using 300-mm silicon photonics technology, initial phase errors between the two arms of each MZ switch are present. Therefore, it is necessary to calibrate these phase errors so that the double-MZ switch elements operate in the cross state (i.e., connections 1–2′ and 2–1′ in Figure 1(a)). The details of this calibration procedure are summarized in the references [35], [36]. In essence, electric power values to set each MZ switch to the bar and cross states are individually identified by varying the input electric power to its thermal phase shifter while monitoring the output power at the corresponding port along the connected path. To avoid interference from light leaking through nonintended paths, it is essential to calibrate the MZ switches in a right order. Given that the 32 × 32 switch contains 2,048 MZ switches, manual calibration is impractical. To address this, we developed and executed a semi-automated calibration program, excluding input port fiber reconnections and polarization adjustments. The total calibration time was approximately 20 h, primarily limited by the communication speed between the control PC, FPGA, and optical power meters. As an example, using a commercially available FPGA together with a monolithically integrated photodetector, 50 measurements can be completed in just 0.4 s [37]. If we build a similar system and apply the recently reported calibration algorithm [35], which requires an average of 7.2 measurements per MZ switch, the calibration of 2,048 switches can be completed in approximately 120 s (calculated as ∼2,048 × 7.2/50 × 0.4).

2.1.2 Optical performance

The optical loss of the fabricated switch was measured for all paths. Light from a cw tunable laser set to a wavelength of 1,322 nm, the center wavelength determined by evaluating test MZ switches fabricated on the same wafer, was coupled into the switch via an optical fiber. The switch was controlled to activate only one target path during each measurement, and all other switches were powered off. The 32 output ports were monitored using four 8-channel optical power meters, and the fiber-to-fiber insertion loss was recorded. The on-chip loss was then calculated by subtracting the coupling loss of 5.5 dB/facet, which was obtained from a coupling loss test waveguide fabricated on the same chip.

Figure 3 shows the distribution of the measured on-chip loss for all paths. Paths that include nonfunctional switches exhibit higher losses. Excluding these paths, the average, minimum, maximum, and standard deviation of the on-chip loss were 11.8 dB, 9.3 dB, 15.6 dB, and 1.1 dB, respectively. Due to the inherent characteristics of the PILOSS topology, all optical paths should exhibit uniform loss. Random variations in the core width may occur across the large die area of 25 mm × 11 mm due to fabrication imperfections. However, we confirmed that the loss variation caused by the random variations is small. In the evaluation of separate chips with many test devices and edge couplers fabricated uniformly, we obtained a small loss variation across the chip (at least smaller than the variation in coupling loss for fiber arrays). Therefore, the observed variation in insertion loss is primarily attributed to fluctuations in coupling efficiency between the optical fibers and the chip, which may be caused by misalignment or bent of the silicon chip, the fiber array, or both, and by variation in the fiber positions within the fiber array. Such variations will be mitigated by using other connection methods such as a silica PLC connector [10], [38]. Since the silica PLC connector can integrate pitch conversion to a narrower pitch, the impact of such variation can be reduced.

Figure 3:

On-chip loss distribution of all paths at a wavelength of 1,322 nm.

Based on the evaluation results of individual test devices fabricated on a separate chip, the detailed loss breakdown for the path with the minimum on-chip loss is summarized in Table 1. As shown in Table 1, propagation loss accounts for a substantial portion of the total loss. Therefore, further reduction of propagation loss is essential for minimizing overall insertion loss.

Next, we evaluated the crosstalk of the fabricated switch. Since the number of switch configurations is 32 factorials, it is infeasible to perform measurements for all possible states. Therefore, we evaluated the worst-case crosstalk scenario, in which the selected optical path intersects with the largest number of other paths. One such configuration is illustrated in Figure 4, where the path from port 3 to port 2′ intersects with the other 31 paths a total of 59 times. To evaluate crosstalk, we first measured the transmitted power through path 3–2′. Subsequently, we configured the switch to have both path 3–2′ and another target path. Light was then injected into the input port of the target path, and the leaked power to output port 2′ was measured. This procedure was repeated for the other 31 paths while varying the wavelength.

Figure 4:

One of the worst crosstalk paths. Path connection setting: input 1 – output 32′, 2–30′, 3–2′, 4–28′, 5–27′, …, 28–4′, 29–3′, 30–29′, 31–1′, and 32–31′. Path 3–2′ has 59 crossings with other paths.

Figure 5 shows the transmission spectrum of the measured path from port 3 to port 2′, along with the wavelength dependence of the total leaked optical power from the other 31 paths to output port 2′. Here, crosstalk is defined as the ratio between these two values. A crosstalk level below −20 dB was achieved for wavelengths of longer than 1.29 µm, with a corresponding bandwidth exceeding 70 nm. Although leakage light from other paths is suppressed over a broad wavelength range, it is necessary to broaden the transmission bandwidth of the path for broadband signal formats such as CWDM4 [39].

Figure 5:

On-chip transmission spectrum of path 3–2′ and sum of leakages spectrum from other paths to port 2′.

Table 2 summarizes the above results in comparison with the key characteristics of previously reported silicon photonic switches operated in the O-band. Various optical switches have been demonstrated using different switching mechanisms and topologies [12], [16], [20], [40]. Among them, our 32 × 32 switch represents one of the largest port counts reported to date. The insertion loss is also relatively low among devices fabricated purely with silicon photonics. Regarding crosstalk, other groups measured the extinction ratio, which is defined as the ratio between the transmitted power in a given path and the highest leaked power to other output ports. In contrast, our measured crosstalk represents performance in more practical operation fully loaded by optical signals. We define it as the ratio between the transmitted power in a given path and the total leaked power from all other paths into that path. Our evaluation method is more stringent, and our switch showed lower crosstalk over a wider spectral range compared to those reported by other groups.

2.2.1 Input and output ports adjacent topology

Figure 6(a) illustrates the input/output port arrangement in conventional switch topologies, where input and output port arrays are placed at the opposite ends. This configuration causes no problems for systems in which optical fibers are used to connect switches and nodes, such as intra/inter data center, and telecom networks. However, this arrangement can pose a challenge in wafer-scale optical interconnects, where many xPUs are interconnected with planar optical waveguides. Figure 6(b) presents an example connection in which eight xPU chiplets are connected through an 8 × 8 optical switch with the conventional input/output port arrangement. An extra length of waveguide and a number of waveguide intersections are required to connect the xPU chiplets to the switch, which lead to increased insertion loss and crosstalk as the port-count increases. To address this issue, switch topologies in which input and output ports are placed adjacent to each other can be used, as illustrated in Figure 6(c) [21]. With this port arrangement, xPU chaplets can be interconnected using simplified wiring, as shown in Figure 6(d). This configuration eliminates the need for long optical waveguide routing and many waveguide intersections, thereby mitigating insertion loss and crosstalk. Following the above observations, we propose a new switch topology, i.e., input and output ports adjacent PILOSS.

Figure 6:

Comparison of xPU connections in conventional optical switches and in switches with adjacent input/output ports. (a) Input and output port arrangement of conventional switch topologies. (b) Example of interconnection between xPUs implemented on the same plane using a conventional switch topology with standard input/output port placement. (c) Input/output port arrangement in the proposed switch topology, where input and output ports are placed adjacent to each other. (d) Wiring configuration between xPUs when using the proposed switch topology.

For simplicity, consider a 4 × 4 PILOSS topology shown in Figure 7(a), where the rear half of the element switches are colored for reference. First, the switch is folded in half along the center line while preserving the connectivity between element switches, as illustrated in Figure 7(b). Next, among the colored switches, those marked in light red are brought to the back of the nonmarked switches located directly beneath them, while the light blue ones remain unchanged, as shown in Figure 7(c). Finally, the switch is unfolded back to its original layout, and the input/output ports are renumbered, resulting in the configuration shown in Figure 7(d). The new switch topology has their input and output ports adjacent to each other. Table 3 summarizes the structural differences between the conventional and proposed PILOSS topologies. The number of element switches on a single path, as well as the number of switches operating in the bar state, remains unchanged. Also, the number of waveguide crossings per path is almost the same (N − 1 and N − 2). Thus, the adjacent port configuration introduces no disadvantages. If any drawback is to be noted, it would be a need for longer routing waveguides on the outer side of the switch. Nevertheless, since these waveguides can mostly be implemented as straight segments, they can be designed with widened low loss structures and are, therefore, not expected to have a significant impact on overall performance.

Figure 7:

Transformation procedure from the conventional path-independent insertion loss (PILOSS) topology to the adjacent input/output port topology. (a) Configuration of the 4 × 4 PILOSS topology. The light red and blue regions in the rear half are used as visual markers. (b) The 4 × 4 switch shown in (a) folded in half. (c) In the folded section, the light red region is swapped with the switch located directly below, while the light blue region remains unchanged. (d) The switch is unfolded after the swapping operation described in (c).

2.2.2 Experimental demonstration

To experimentally validate the proposed topology with adjacent input/output ports, we fabricated an 8 × 8 switch with the topology. Figure 8 shows an optical microscope image of the fabricated chip. Similar to the 32 × 32 switch described in the previous subsection, the device was designed for the TE-mode and the O-band and fabricated using our 300-mm silicon photonics pilot line. Each element switch is a heater-controlled MZ switch. To reduce the number of electrodes, a standard single MZ switch element was used instead of the double-MZ switch element. The fabricated chip was die-bonded onto a ceramic chip carrier, and wire bonding was used to connect the electrode pads on the chip to those on the carrier. The carrier electrodes were routed through a PCB to a 64-channel digital analog converter (DAC) array. Electrical power supplied to each switch heater was controlled via a PC connected to the DAC array. For optical interfacing, edge couplers were grouped on one side of the chip, and an 18-channel high-NA (MFD: 4.0 μm at a wavelength of 1.31 µm) fiber array was butt-coupled to them. Based on evaluation of test patterns, the coupling loss between the fiber and chip was measured to be 4 dB/facet. Similar to the 32 × 32 switch, the 8 × 8 switch also requires calibration of the initial phase errors between the arms of each MZ switch. While the basic procedure remains the same, the 8 × 8 switch contains only 64 MZ switches, making manual calibration sufficiently feasible.

Figure 8:

Fabricated chip of input and output ports adjacent 8 × 8 switch.

Using a tunable laser diode and an 8-channel optical power meter, we measured the fiber-to-fiber insertion loss of all paths. The results are shown in Figure 9. The average, minimum, maximum, and standard deviation of the fiber-to-fiber insertion loss were 8.8 dB, 5.8 dB, 12.3 dB, and 1.5 dB, respectively. As with the 32 × 32 switch, this variation is primarily attributed to variation in coupling loss between the optical fibers and the chip. According to the port-by-port loss distribution, the coupling loss was lower near the center of the fiber array and tended to increase toward the edges. This suggests that either the fiber array, the chip, or both may be slightly bent at the center.

Figure 9:

Distribution of fiber-to-fiber insertion loss of all paths.

Next, we evaluated crosstalk. Figure 10 illustrates one of the worst crosstalk paths within all paths of the proposed 8 × 8 switch. The path from input port 3 to output port 4′ traverses the left half of the switch matrix and folds back, crossing with the other paths a total of ten times. Figure 11 presents the transmission spectrum of path 3–4′, along with the wavelength-dependent sum of leaked light from the other paths that outputs at port 4′. Defining crosstalk as the ratio between these two spectra, the wavelength range in which the crosstalk remains below −20 dB was found to be 4 nm. Due to limitations in the number of available electrodes, single MZ switch elements were employed in this 8 × 8 switch. This resulted in relatively high crosstalk and a narrow operational bandwidth. If double-MZ switch elements were used instead, as demonstrated in our previous 8 × 8 switch [29], it is expected that a crosstalk of −30 dB could be achieved over a bandwidth exceeding 70 nm.

Figure 10:

One of the worst crosstalk paths. Path connection setting: input 1 – output 8′, 2–7′, 3–4′, 4–1′, 5–6′, 7–3′, and 8–2′. Path 3–4′ has 10 crossings with other paths.

Figure 11:

On-chip transmission spectrum of path 3–4′ and sum of leakages spectrum from other paths to port 4′.