Reconfigurable Wide Input Range, Fully-Differential Indirect Current-Feedback Instrumentation Amplifier with Digital Offset Calibration for Self-X Measurement Systems

1 Introduction

The up-to-date enormous application fields such as Industry 4.0, I(I)oT , CP(p)S and intelligent systems introduce more demands on sensors and sensor electronics, mainly regarding measurement accuracy, flexibility, versatility, robustness and long term reliability [12, 14]. Generally, sensor electronics, more specifically, the integrated circuits (ICs) in advanced technology, are significantly subjected to both, static and dynamic deviations. The static deviations can be due to fabrication imperfection such as process parameters variations [24], lithographic uncertainties [18], mechanical stress induced by packaging [4], etc. Whereas, the dynamic deviations after manufacturing can occur due to environmental variations (temperature, humidity), changes in supply voltage, thermal drift caused by the IC self-heating [28] and aging effects [16]. Several techniques can be followed to tackle IC deviations in the early design time of the circuit or after manufacturing. Layout matching techniques during design phase are intensively used to treat static deviations caused by random process variations in which common centroid or interdigitized layout with the aid of dummy elements are used to average the expected fabrication tolerances equally between matched devices [8]. Nevertheless, systematic errors from the design itself add another type of static error to the circuit and needs a more sophisticated and dynamic calibration approaches to alleviate, e.g., auto-zero or chopping are prevalent methods to cancel the offset voltage error of the operational amplifiers after fabrication [6, 7]. Also, Laser and Zener zapping trimming are traditional onetime adjustment techniques used at the wafer level, but due to cost and unaffordability, it cannot be applied in new CMOS technology [21, 35], nor it can dynamically adjust the circuit drifts appears after IC packaging. Dynamic deviations, especially that related to the aging effect (drift over time) are difficult to predict or mitigate [32], thus it imposes the need of a configurable circuit design with self-X capabilities (self-calibrating, healing/repairing, trimming, monitoring) to adjust the circuit [5, 9, 12, 19, 20] adaptively and continuously. Both auto-zero and chopping techniques are dynamic correction approaches. However, they are limited to correct offset or noise, while self-X term is a more general approach to correct for any type of error. More precisely, self-X electronic system is evolvable hardware (EHW) that can be dynamically adapted and reconfigured to compensate for deviations. EHW refers to the self- reconfiguration of the reconfigurable electronic hardware (digital/analog) by evolutionary optimization algorithms (EA) such as Genetic Algorithm (GA), Particle Swarm Optimization (PSO) [29]. These smart algorithms run on the digital domain to optimally resynthesize the system hardware to adapt dynamically for faults or deviations. As a result, the updated system will be able to maintain/recover the running/ lost functionality. The concept of self-X leads to achieving reliable and robust systems with high immunity and manufacturing yield, hence, satisfying the conditions of industry 4.0 requirements [30]. Not exclusively for calibrating, but the same approach can be employed to change the system performance to meet different signal or user demands, omitting the need for replacing the hardware. The early contribution to the self-X work was presented by authors in [17, 22]. Authors in [10, 12, 19, 20] further extended the concept of self-X beyond the readout circuit to correct the drifts of the sensor elements or the sensor bridge as well.

2 Objectives

The primary goal of this paper is to design a robust and flexible analog readout sensory circuit to support self-X properties for industry 4.0 applications. The proposed circuit diagram shown in (Fig. 1) is a configurable wide input-range fully-differential instrumentation amplifier (InAmp) based on indirect current-feedback technique [2, 27, 31], as a further improvement to our previous work presented in [1] combined with our work in [33, 34]. The main improvements achieved in this work as comparing to [1] is regarding circuit programmability with the aid of EA and the introduction of offset calibration scheme in the design. Hence this circuit is suitable to interface small and large sensor signals.

Fig. 1

Proposed configurable CFIA with digital offset correction.

Configurability is achieved by designing a digital weighted element (binary or thermometer coded) array of the targeted device in the circuit controlled digitally by CMOS switches [15]. The digital processing unit (computer in this work) running the EA generates the configuration bitstream delivered to the circuit in serial form and saved in shift registers. The flexibility of the fully configurable circuit comes with the cost of 1) bigger die area due to elements arrays, switches and storage part, which leads to rising the fabrication cost or reducing the number of circuits per chip. 2) Larger parasitics that limit the dynamic performance. 3) Longer configuration and optimization time. For the mentioned reasons, we propose to configure only the sensitive elements in the circuit that have essential impact control on the targeted specification as given in (Tab. 1), achieved by 100 bits. To evade sparks and ripples on the output signal associated with auto-zeroing and chopping techniques due to switches charge injection and clock feedthrough, plus the complexity of treating it [26], we propose a new approach based on digital offset trimming, inspired by the work presented in [3, 13, 25], offset self-calibrating from Texas Instrument [23] and DigiTrim® technology from Analog Devices [35]. Authors in [24] refer to the digital offset trimming as digital auto-zero. In the proposed method, a configurable input transconductance (G_mos) is added in parallel to the primary inputsand feedback transconductances (G_m1,G_m2) of the InAmp, as presented in (Fig. 1). The details of the proposed approach are depicted in (Fig. 2).

Fig. 2

Proposed digital offset trimming of the CFIA.

During phase A, the In-Amp inputs are disconnected from the sensor and shorted to the common-mode voltage (V_CM) while the output is disconnected from the proceeding stage. In this phase, the input offset voltage (V_OS) is presented at the output amplified by the closed-loop gain of the In-Amp, usually set to unity. The optimization unit read this voltage from the analog-to-digital converter (ADC) and run the EA targeting G_mso. The latter one is designed with configurable current source and differential pair transistors as well. EA will continue to perturb both the balance of the differential pair and the current source until the current at the summing node in the main In-Amp nulls completely the offset current between the feedback and the input transconductances, consequently, nulling the offset voltage. The use of configurable current source allows the EA to search for the solution more efficiently and can adjust more precisely for low and large offset voltages. In phase B, the In-Amp returns to the amplification mode and the offset configuration bits is saved in the shift register for an un-limited time as long as the circuit is powered on or until next phase of compensation if it is required. In contrast to the auto-zeroing/chopper techniques where periodic/continuous adjustment is necessary. Because the ADC and the processing unit are already employed in the self-X system, the complexity of including these units is not counted for the proposed offset correction scheme. The minimum trimming offset voltage is limited to the resolution and the accuracy of the used ADC. However, trimming an offset voltage smaller than the resolution of the ADC can be achieved by setting the In-Amp at a higher gain value. In principle, a well-trained and tested configuration bits for different conditions can be saved and addressed directly to the In-Amp without the need of running the EA, thus, saving the calibration time. Digital offset trimming approach has no capacitor element to share with the input or output signal path. Therefore it does not influence the dynamic amplifier performance. Consequently, the In-Amp can work with high bandwidth as intended in our targeted application. The digital offset trimming has another advantage that is suitable for both sampled and continuous-time circuits.

3 Design Methodology

Based on the basic knowledge about the circuit and the results obtained during the simulation and optimization process with EA, the only critical and sensitive elements are nominated for reconfigurability. In the circuit operation, EA will take control of the configurable elements, where other elements in the circuit are fixed to the optimized values.Transistor level design of the In-Amp core is given in (Fig. 3). For the paper size constrains, The biasing and the common mode feedback (CMFB) circuits are not presented. The circuit support the power down scheme shown by blue coloured transistors.

Fig. 3

Fully-differential CFIA core circuit.

(Fig. 4) shows the schematic design of the scalable PMOS transistor array, scalable resistor and capacitor used to realize the design. for the PMOS array, the length of the transistors are fixed to 1 μm, and the aspect ratios changes in the power of two (binary-weighted). The length of the MOS switches are set to minimum (0.35 μm). The gate of the unselected transistor in the array are shorted to V_DD to avoid floating gate problem and guarantee the transistor is fully off. In case of fractional combination is required to implement more precise MOS biasing diodes, two transistors with length equal to 2 μm are added to the array for fine adjustment.

Fig. 4

Scalable devices (a) PMOS transistor (b) capacitor (c) resistor.

The scalable NMOS transistor array is constructed in a similar way to PMOS counterpart but with gate shorted to ground for the unselected transistor. The Programmable feedback resistor is designed much the same of digital potentiometer tapped at defined steps. Bank of selectable capacitors arranged in binary-weighted array is used to design the programmable compensation capacitor. Yet, CMOS complementary switches are chosen in the programmable elements because it provides better linearity and less on resistance. Two programmable current mirrors in the circuit are slightly implemented differently from the scalable MOS transistor. (Fig. 5) depicts the main programmable current mirror used to source the In-Amp from the reference current source and designed in binaryweighted form. The designed mirror uses only one simple switch at each mirror branch, hence saving more area.

Fig. 5

Main programmable biasing current mirror.

The non-linearity of the simple switch resistance does not influence the circuit performance because it passes biasing current not a signal. However, the voltage drop across the switch ON resistance should be considered to leave safe headroom for the cascoded transistors to work in the saturation region. Therefore, switch size is scaled with the mirror branch order. The programmable current mirror used to source G_mso is constructed by using thermometer binary-coded, as shown in (Fig. 6). Thermometer coding is more precise digital coding and has less glitching noise [11] as comparing to binary-weighted one, which is especially useful to adjust more precisely for offset voltage.

Fig. 6

Programmable current mirror for G_mso unit.

The AC open-loop simulation of the circuit is shown in (Fig. 7) under different set of bit configurations. In the practical application, if the phase shift for example is becoming critical, EA will adapt a new value of compensation capacitor (CC) and stabilize the circuit. In similar way, the GBW can be increased by increasing the biasing current or reducing the CC if there is enough phase margin. The output voltages from DC simulation of the circuit is depicted in (Fig. 8) with the programmable gain setting (1, 2, 4, 8), it shows the circuit accepting a wide differential input span. The high programmable GBW and wide amplifier input range candidate the proposed design as an excellent solution to interface fast and large sensor signals like tunnel-magnetoresistive (TMR) sensor signal and other types of fast sensor signals. The programmable CC can be reduced at higher closed-loop gain to extend the GBW where the phase margin is less critical as shown in (Fig. 9). The setup is evaluated at gain equal to 24 dB and CC is swept between 200 fF and 3.2 pF.

Fig. 7

In-Amp AC simulation for several configuration patterns.

Fig. 8

Programmable gain In-Amp at different values.

Fig. 9

In-Amp bandwidth as function to CC with gain = 24 dB.

4 Conclusion

In this paper, a programmable In-Amp based on CFIA and digital-offset trimming is presented. To save the area, configuration time and obtaining high speed In-amp, a selected elements from the circuit are made programmable. Long term reliability and robustness of the circuit by using self-X concept make it good choice for industry 4.0 application. Programmability of the circuit serve for circuit adjustment for a targeted specification or to change the circuit properties to fit different demands. The digital assessment unit with other required subcircuits is part of future design work, together by shifting to XFAB technology. Design methodology followed in this paper will be further extended to the remaining analog parts of the interface circuit, e.g. active antialiasing filter, etc. Sensitivity analyses from Cadence tools will be investigated in our next work to more accurately identify the critical elements in the circuit for reconfigurability.