Volume 6, Issue 3-4 - Optical Nanostructuring / Guest Editors: Jan van Schoot, Helmut Schift

Road mapping of semiconductor chips has been underway for over 20 years, first with the International Technology Roadmap for Semiconductors (ITRS) roadmap and now with the International Roadmap for Devices and Systems (IRDS) roadmap. The original roadmap was mostly driven bottom up and was developed to ensure that the large numbers of semiconductor producers and suppliers had good information to base their research and development on. The current roadmap is generated more top-down, where the customers of semiconductor chips anticipate what will be needed in the future and the roadmap projects what will be needed to fulfill that demand. The More Moore section of the roadmap projects that advanced logic will drive higher-resolution patterning, rather than memory chips. Potential solutions for patterning future logic nodes can be derived as extensions of ‘next-generation’ patterning technologies currently under development. Advanced patterning has made great progress, and two ‘next-generation’ patterning technologies, EUV and nanoimprint lithography, have potential to be in production as early as 2018. The potential adoption of two different next-generation patterning technologies suggests that patterning technology is becoming more specialized. This is good for the industry in that it lowers overall costs, but may lead to slower progress in extending any one patterning technology in the future.

The evolutionary advances in photosensitive material technology, together with the shortening of the exposure wavelength in the photolithography process, have enabled and driven the transistor scaling dictated by Moore’s law for the last 50 years. Today, the shortening wavelength trend continues to improve the chips’ performance over time by feature size miniaturization. The next-generation lithography technology for high-volume manufacturing (HVM) is extreme ultraviolet lithography (EUVL), using a light source with a wavelength of 13.5 nm. Here, we provide a brief introduction to EUVL and patterning requirements for sub-0-nm feature sizes from a photomaterial standpoint, discussing traditional and novel photoresists. Emphasis will be put on the novel class of metal-containing resists (MCRs) as well as their challenges from a manufacturing prospective.

Extreme ultraviolet (EUV) lithography is expected to succeed in 193-nm immersion multi-patterning technology for sub-10-nm critical layer patterning. In order to be successful, EUV lithography has to demonstrate that it can satisfy the industry requirements in the following critical areas: power, dose stability, etendue, spectral content, and lifetime. Currently, development of second-generation laser-produced plasma (LPP) light sources for the ASML’s NXE:3300B EUV scanner is complete, and first units are installed and operational at chipmaker customers. We describe different aspects and performance characteristics of the sources, dose stability results, power scaling, and availability data for EUV sources and also report new development results.

The reflection and diffraction of extreme ultraviolet (EUV) light from lithographic masks and the projection imaging of these masks by all-reflective systems introduce several significant imaging artifacts. The off-axis illumination of the mask causes asymmetric shadowing, a size bias between features with different orientations and telecentricity errors. The image contrast varies with the feature orientation and can easily drop far below intuitively expected values. The deformation of the wavefront or phase of the incident light by thick absorbers generates aberration-like effects, especially variations of the best-focus (BF) position vs. the pitch and size of the imaged patterns. Partial reflection of light from the top of the absorber generates a weak secondary image, which superposes with the main image. Based on a discussion of the root causes of these phenomena, we employ mask diffraction and imaging analysis for a quantitative analysis of these effects for standard EUV masks. Simulations for various non-standard types of mask stacks (e.g. etched multilayers, buried shifters, etc.) and for various non-standard absorber materials are used to explore the imaging capabilities of alternative masks for EUV lithography. Finally, an outlook at anamorphic systems for larger numerical apertures is given.

This article covers the various aspects of defectivity of a typical mask used for extreme ultra-violet (EUV) lithography. The focus of the present article is on those aspects that are more specific for EUV lithography. A prime type of defect that fully falls under the really EUV-specific category consists of the so-called multilayer defects (ML-defects): these defects relate to the ML mirror on the mask, which makes it reflective. While not specific, particle contamination plays a special role in EUV lithography and includes two aspects: both front- and backside of an EUV mask have peculiarities beyond historical deep-UV lithography. Frontside particles can print when they exceed a critical size and, while solvable as in (deep)-UV lithography by means of a pellicle, there are specific challenges. Backside particles can distort a clamped EUV reticle, and the resulting local non-flatness of the reticle may result in focus and overlay errors on the wafer. A last aspect that requires special attention for EUVL can be categorized under reticle degradation by extensive use. That includes the high-volume manufacturing-oriented conditions of high source power needed to obtain competitive throughput. For each aspect of EUV mask defectivity, and hence each type of defect, the paper reviews how the community tackles them and how their possible impact on the result of wafer printing with a given EUV reticle is minimized. This includes a summary of the authors’ own contribution to related learning and developments. Finally, a personal interpretation is given of what are the remaining open items before a workable or full solution can be considered in place.

In a lithography process, an image on a mask (reticle) is projected onto a wafer. Continuous decrease in feature sizes also led to a reduction in the wavelength used for exposing. The next step is the move from 193-nm light to extreme ultra-violet (EUV) at 13.5 nm. This poses a lot of challenges that have been overcome in the past years. One of these challenges is the protection of the reticle from front side defects. This protection can be achieved by the use of an EUV pellicle. This is a thin membrane that protects particles from landing on the reticle surface, as will be explained in more detail later. With multiple semiconductor manufacturers preparing for volume EUV manufacturing, the need for a volume production-ready pellicle solution is here today. This article gives an overview of the performance of the current EUV pellicle solution and the status of the development of future EUV pellicles.

Imprint lithography has been shown to be a promising technique for the replication of nanoscale features. Jet and flash imprint lithography (J-FIL) [jet and flash imprint lithography and J-FIL are trademarks of Molecular Imprints, Inc.] involves the field-by-field deposition and exposure of a low-viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid, which then quickly flows into the relief patterns in the mask by capillary action. After this filling step, the resist is cross-linked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are many criteria that determine whether a particular technology is ready for wafer manufacturing. Included on the list are overlay, throughput, and defectivity. The most demanding devices now require an overlay of better than 4 nm, 3σ. Throughput for an imprint tool is generally targeted at 80 wafers/h. Defectivity and mask life play a significant role relative to meeting the cost of ownership (CoO) requirements in the production of semiconductor devices. The purpose of this paper is to report the status of throughput and defectivity work and to describe the progress made in addressing overlay for advanced devices. To address high-order corrections, a high-order distortion correction (HODC) system is introduced. The combination of applying magnification actuation to the mask and temperature correction to the wafer is described in detail. Examples are presented for the correction of K7, K11, and K17 distortions as well as distortions on actual device wafers.

Releasing the potential of advanced material properties by controlled structuring materials on sub-100-nm length scales for applications such as integrated circuits, nano-photonics, (bio-)sensors, lasers, optical security, etc. requires new technology to fabricate nano-patterns on large areas (from cm 2 to 200 mm up to display sizes) in a cost-effective manner. Conventional high-end optical lithography such as stepper/scanners is highly capital intensive and not flexible towards substrate types. Nanoimprint has had the potential for over 20 years to bring a cost-effective, flexible method for large area nano-patterning. Over the last 3–4 years, nanoimprint has made great progress towards volume production. The main accelerator has been the switch from rigid- to wafer-scale soft stamps and tool improvements for step and repeat patterning. In this paper, we discuss substrate conformal imprint lithography (SCIL), which combines nanometer resolution, low patterns distortion, and overlay alignment, traditionally reserved for rigid stamps, with the flexibility and robustness of soft stamps. This was made possible by a combination of a new soft stamp material, an inorganic resist, combined with an innovative imprint method. Finally, a volume production solution will be presented, which can pattern up to 60 wafers per hour.

Fabrication of two- and three-dimensional (2D and 3D) structures in the micro- and nano-range allows a new degree of freedom to the design of materials by tailoring desired material properties and, thus, obtaining a superior functionality. Such complex designs are only possible using novel fabrication techniques with high resolution, even in the nanoscale range. Starting from a simple concept, transferring the shape of an interference pattern directly to the surface of a material, laser interferometric processing methods have been continuously developed. These methods enable the fabrication of repetitive periodic arrays and microstructures by irradiation of the sample surface with coherent beams of light. This article describes the capabilities of laser interference lithographic methods for the treatment of both photoresists and solid materials. Theoretical calculations are used to calculate the intensity distributions of patterns that can be realized by changing the number of interfering laser beams, their polarization, intensity and phase. Finally, different processing systems and configurations are described and, thus, demonstrating the possibility for the fast and precise tailoring of material surface microstructures and topographies on industrial relevant scales as well as several application cases for both methods.

To evaluate the maturity of the wafer-scale NanoImprint lithography (NIL) process, laboratory of electronic and communication technology (LETI) and EV Group (EVG) launched the Imprint Nanopatterning Solution Platform for Industrial Assessment program (INSPIRE), which aims at building a nanoimprint solution platform for industrial assessment and provide a unique open ecosystem for the standardization of the nanoimprint process. This program enabled to gather EVG know-how for the tool manufacturing and its long expertise in bonding activities, and the established methods and advanced microelectronic environment. Presented as an upstream phase, metrology and defectivity were performed on dedicated assessment designs to address critical dimension uniformity (CDU) at wafer scale for a large number of imprints, defectivity on imprints and masters, and alignment capabilities of the nanoimprint HERCULES® platform of EVG. We demonstrate that the critical points are the anti-sticking layer for the defectivity, the CD shrinkage for the CDU, and the stiffness of the soft stamp for the overlay uniformity. Thus, we bring to light the actual capabilities of the HERCULES® platform, and open the discussions on the opportunities for this technology with the possible improvements for the process.

Chip makers are actively working on the adoption of 0.33 numerical aperture (NA) EUV scanners for the 7-nm and 5-nm nodes (B. Turko, S. L. Carson, A. Lio, T. Liang, M. Phillips, et al., in ‘Proc. SPIE9776, Extreme Ultraviolet (EUV) Lithography VII’, vol. 977602 (2016) doi: 10.1117/12.2225014; A. Lio, in ‘Proc. SPIE9776, Extreme Ultraviolet (EUV) Lithography VII’, vol. 97760V (2016) doi: 10.1117/12.2225017). In the meantime, leading foundries and integrated device manufacturers are starting to investigate patterning options beyond the 5-nm node (O. Wood, S. Raghunathan, P. Mangat, V. Philipsen, V. Luong, et al., in ‘Proc. SPIE. 9422, Extreme Ultraviolet (EUV) Lithography VI’, vol. 94220I (2015) doi: 10.1117/12.2085022). To minimize the cost and process complexity of multiple patterning beyond the 5-nm node, EUV high-NA single-exposure patterning is a preferred method over EUV double patterning (O. Wood, S. Raghunathan, P. Mangat, V. Philipsen, V. Luong, et al., in ‘Proc. SPIE. 9422, Extreme Ultraviolet (EUV) Lithography VI’, vol. 94220I (2015) doi: 10.1117/12.2085022; J. van Schoot, K. van Ingen Schenau, G. Bottiglieri, K. Troost, J. Zimmerman, et al., ‘Proc. SPIE. 9776, Extreme Ultraviolet (EUV) Lithography VII’, vol. 97761I (2016) doi: 10.1117/12.2220150). The EUV high-NA scanner equipped with a projection lens of 0.55 NA is designed to support resolutions below 10 nm. The high-NA system is beneficial for enhancing resolution, minimizing mask proximity correction bias, improving normalized image log slope (NILS), and controlling CD uniformity (CDU). However, increasing NA from 0.33 to 0.55 reduces the depth of focus (DOF) significantly. Therefore, the source mask optimization (SMO) with sub-resolution assist features (SRAFs) are needed to increase DOF to meet the demanding full chip process control requirements (S. Hsu, R. Howell, J. Jia, H.-Y. Liu, K. Gronlund, et al., EUV ‘Proc. SPIE9048, Extreme Ultraviolet (EUV) Lithography VI’, (2015) doi: 10.1117/12.2086074). To ensure no assist feature printing, the assist feature sizes need to be scaled with λ/NA. The extremely small SRAF width (below 25 nm on the reticle) is difficult to fabricate across the full reticle. In this paper, we introduce an innovative ‘attenuated SRAF’ to improve SRAF manufacturability and still maintain the process window benefit. A new mask fabrication process is proposed to use existing mask-making capability to manufacture the attenuated SRAFs. The high-NA EUV system utilizes anamorphic reduction; 4× in the horizontal (slit) direction and 8× in the vertical (scanning) direction (J. van Schoot, K. van Ingen Schenau, G. Bottiglieri, K. Troost, J. Zimmerman, et al., ‘Proc. SPIE. 9776, Extreme Ultraviolet (EUV) Lithography VII’, vol. 97761I (2016) doi: 10.1117/12.2220150; B. Kneer, S. Migura, W. Kaiser, J. T. Neumann, J. van Schoot, in ‘Proc. SPIE9422, Extreme Ultraviolet (EUV) Lithography VI’, vol. 94221G (2015) doi: 10.1117/12.2175488). For an anamorphic system, the magnification has an angular dependency, and thus, familiar mask specifications such as mask error factor (MEF) need to be redefined. Similarly, mask-manufacturing rule check (MRC) needs to consider feature orientation.

Present-day thermode bond systems for the assembly of radio-frequency identification (RFID) chips are mechanically inflexible, difficult to control, and will not meet future manufacturing challenges sufficiently. Chip bonding, one of the key processes in the production of integrated circuits (ICs), has a high potential for optimization with respect to process duration and process flexibility. For this purpose, the technologies used, so far, are supposed to be replaced by a transmission laser-bonding process using low-melting eutectic alloys. In this study, successful bonding investigations of mock silicon chips and of RFID chips on flexible polymer substrates are presented using the low-melting eutectic alloy, 52In48Sn, and a laser with a wavelength of 2 μm.