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A Compact Four Transistor CMOS-Design of a Floating Memristor for Adaptive Spiking Neural Networks and Corresponding Self-X Sensor Electronics to Industry 4.0

  • Hamam Abd EMAIL logo and Andreas König
Published/Copyright: August 28, 2020
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tm - Technisches Messen
From the journal tm - Technisches Messen Volume 87 Issue s1

Abstract

In this work we present, in the context of the transition from amplitude to robust spike domain sensing and electronics, a floating memristor. It can be used to construct memristor SNNs used for noise-robust conditioning and analog-to-digital conversion and manufactured using leading-edge technologies with more ’cranky’ devices, low-voltage, low power, and minimal area on-chip. Also, this supports both machine learning as well as the self-x properties in advanced sensor electronics system for industry 4.0. The proposed memristor has less design complexity and a higher number of resistance levels as compared to other existing memristors. The proposed CMOS memristor is designed using AMS 0.35 μm CMOS technology and Cadence design tools. Its layout occupies an area of 70 μm × 85 μm. The simulation shows the performance of the proposed floating memristor emulator in the temperature range (-40 °C to 85 °C) and Monte-Carlo simulation.

Zusammenfassung

In dieser Arbeit stellen wir im Kontext des Übergangs von einer Amplituden-zur robusten Pulsbereichsrepräsentation und Sensorelektronik, eine Floating-Memristor-Schaltung vor. Diese soll als Synapsenelement der Erstellung von adaptiven pulsenden Neuronennetzen dienen, die Sensorsignalkonditionierung und -nach-Digitalwandlung robust gegenüber Herstellungsschwankungen, sinkenden Betriebsspanunngen und reduziertem Aussteuerbereich, Verlustleistungs- und Flächenmimimierungsforderungen sowie Störeinflüßen erlauben und damit auch in modernsten Herstellungstechnologien mit Bauelementen sinkender Zuverlässigkeit zu lebensfähigen Sensorelektronik-Chips führen. Mit der dann gegebenen Adaptivität wird sowohl das Maschinelle Lernen unterstützt als auch die Forderung an Self-x-Eigenschaften der fortgeschrittenen Sensorelektronik für die Industrie 4.0 erfüllt. Der vorgeschlagene Memristor hat eine geringere Entwurfskomplexität und eine höhere Anzahl einstellbarer Widerstandsstufen im Vergleich zu anderen bestehenden Memristoren. Der CMOS-Memristor wurde in der AMS 0.35 um CMOS-Technologie mit der Cadence-Entwurfsumgebung entworfen. Das zugehörige Layout belegt eine Fläche von 70 μm × 85 μm. Die Simulation bestätigt die Leistungsfähigkeit der vorgeschlagenen Floating-Memristor-Schaltung im Temperaturbereich -40°C bis 85°C und einer Monte-Carlo-Analyse.’

Keywords: Frequency sensory; Memristor; Memristor neuromorphic architectures; Adaptive synapse; Adaptive spiking neural network; Self-x properties; Machine learning; Sensor electronics system; Industry 4.0
Schlüsselwörter: Frequenzsensorik; Memristor; Neurmorphe Memristor-Architekturen; Adaptive Synapsen; Adaptives pulsendes neuronales Netzwerk; Self-x-Eigenschaften; Maschinelles Lernen; Sensorelektroniksystem; Industrie 4.0

1 Introduction

In the last few years, the number of edge devices in IoT and industry 4.0 has been increased leading to a growth in machine learning as well as the urgent need for self-x (self-healing, self-calibration) technology [1, 37, 38]. Issues of leading-edge technologies for integrated sensor electronics advocate the transition from amplitude to time or spike domain information processing. Inspirations from frequency sensors and adaptive spiking neural networks can be employed for resilient/self-x system realizations. A key mandatory element is a programmable or adaptive synapse, e.g. by a memristor realization. On the other hand, the memristor neuromorphic architectures learning, self-x, scalability, have a low power profile and small onchip footprint [20]. Currently, this technique became a promising solution for edge devices. Although many memristor neuromorphic architectures were proposed in the sensing system, however, the memristor SNNs (Spiking Neural Network) have a lower power profile and more robust to the noise since they encode the information using the spike times and process only when the events occur [31]. Also, from the mechanisms function view, since the SNNs use the time domain encoding (noise-robust) and have the capability of learning and self-x, they solve one of the main problems in the sensing system where the output noise of the sensor could lead to an indirect error in the measurements [31].

A lucid example of adaptive SNN are delay lines in acoustic localization, as shown in (Fig. 1) [14, 15, 16, 19]. The brain determines the location of the sound by the difference time of ears = t1−t2 where t1 and t2 are the times of the sound reaching the right and left ears, respectively as shown in (Fig. 1 A). The neural network in (Fig. 1 B) mimics the sound location detection by the brain. The network consists of two sensors, and each sensor represents one ear, two neurons, and two synapses. The first and the second neuron fire responds to the right and the left, respectively. The neuron spikes when the membrane voltage is greater than the threshold voltage, as shown in the (Fig. 1 B). The synapses adaptively control the amount of the charge to the neuron by adapting the spike. Consequently, the synapses control the time delay at where the neurons will be spiked. The delay can be controlled by changing the weights of the synapses. These synapses are programmed with a certain weight to keep it constant under variations/perturbations. The synapses can be emulated by a memristor with one transistor (1T1M).

Fig. 1 (A) Acoustic localization model. (B) SNN schematic structure of equivalent conversion concept.
Fig. 1

(A) Acoustic localization model. (B) SNN schematic structure of equivalent conversion concept.

A memristor is a two-terminal device where the resistance value of the memristor is dependent on the polarity and magnitude of the applied voltage and the length of time that voltage has been applied [8]. As reviewed in the literature, the memristor concept was suggested by Leon Chua in 1971[8]. However, researches could not evaluate the memristor until it was implemented by Hewlett Packard (HP) in 2008 [29]. Even though many benefits gained from using the memristors in much application such as neuromorphic circuits[20], programmable analog circuits[24], chaotic circuits[23], adaptive filters[9], basic arithmetic operations[18], sensory electronics system, internet of things (IoT), machine learning[12], they are not expected to be used in the commercial chip soon because of many open problems that need tobe investigated, such as the fabrication complexity of memristor systems, unstable switching behavior, the finite number of resistor levels, and compatibility with CMOS technology [20]. To implement neuromorphic architectures and integrated on the real chips, therefore, the researchers have focused on memristor emulators [2, 3, 4, 5, 6, 10, 17, 27, 28, 30, 32, 33, 34, 35, 36]. State-of-the-art designs cannot integrate on-chip memristor because they have complex circuits and need an external devices. They are used a lot of active components and passive elements [2, 3, 4, 5, 6, 10, 17, 27, 28, 30, 32, 33, 34, 35, 36]. Some of them have grounded structures [2, 6, 10, 17, 32, 34, 35], and others have floating structures [3, 4, 5, 27, 28, 30, 33, 36]. Designing a floating memristor circuit is more complex than designing a grounded memristor circuit; however, grounded memristor has limited applications. In [17], authors proposed grounded memristor with two operational amplifiers, ten transistors, two resistors, a capacitor and multiplier. Also, in [2], they proposed grounded memristor emulator circuit using current backward transconductance amplifier (CBTA), multiplier, two resistors and a single capacitor. Additionally, in [6], they proposed grounded memristor emulator with four transistors. Likewise, in [10], he proposed grounded memristor emulator with four transistors. Similarly, in [32] he proposed grounded memristor emulator with seven transistors and a single capacitor. Moreover, in [35] they proposed grounded memristor emulator circuit using voltage differencing current conveyor (VDCC), two transistors and a single capacitor. As well, in [34] they proposed grounded memristor emulator circuit using voltage difference transconductance amplifier (VDTA), single transistors. In [28], floating memristor emulator circuit was proposed using three operational transconductance amplifiers (OTA), four second-generation current conveyors (CCII), six resistors and a single capacitor. Also, in [5] floating memristor was proposed with MO-OTA, resistor, capacitor, and multiplier. Besides, in [30] floating memristor was proposed with three transistors, external capacitor and a current source. Also, in [36] they proposed a floating memristor emulator circuit using current backward transconductance amplifier (CBTA) with two capacitors. Likewise, in [4] they proposed floating memristor with single OTA, two transistors and an external capacitor. Moreover, in [3] they proposed floating memristor with ten transistors and three external capacitors. Additionally, in [33] they proposed floating memristor emulator circuit using differential difference current conveyor (DDCC) two resistors, capacitor and multiplier. Furthermore, in [27] they proposed a floating memristor emulator circuit, which is built with four second-generation current conveyors (CCII) and single multiplier.

The primary objective of this research is to design a memristor that can be on-chip integrated without needing any external components. The target is to construct an adaptive synapse and an adaptive spiking neuron. These will serve to construct memristor-based adaptive SNNs, that introduce machine learning to support sensor electronics with self-x properties as demanded by industry 4.0.

2 Proposed Methodology

In this research, we design a compact floating memristor emulator circuit consisting of only four CMOS transistors, as shown in (Fig. 2).The proposed memristor has the following distinguishing features as compared to the other work presented in [2, 3, 4, 5, 6, 10, 17, 27, 28, 30, 32, 33, 34, 35, 36] : 1) less complexity. 2) can be on a chip integrated. 3) does not need any external device. 4) has a high number of resistor levels. The drain-to-source resistance of MOSFET (M1) represents the resistance of the memristor, which is changing by the voltage across the transistor M4. M4 is conecting as a capacitor by tying the drain, source, and bulk to Vss [26]. M2 and M3 transistors are the feedback circuit that controls the voltage across M4. The feedback circuit is controlled by external voltage sources (VA, VB).

Fig. 2 Proposed emulator memristor circuit and its symbol.
Fig. 2

Proposed emulator memristor circuit and its symbol.

3 Results

The proposed memristor is simulated using spectre simulator from Cadence. AMS 0.35 μm CMOS technology is used, and the power supply voltages of the circuit are Vdd = −Vss = 1.65V. The aspect ratios of the transistors are designed as (W/L)M1 = 30 μm/0.35 μm, (W/L)M2 = 3 μm/2 μm, (W/L)M3 = 2 μm/3 μm, and(W/L)M4 = 80 μm/60 μm. In order to draw the voltage-current characteristic of the proposed floating memristor, the sinusoidal signal has been applied to it, as shown in (Fig. 3).

Fig. 3 The test circuit of the memristor characteristics.
Fig. 3

The test circuit of the memristor characteristics.

The voltage-current characteristic of the proposed floating memristor for 2 MHz frequency is shown in (Fig. 4).

Fig. 4 The voltage-current characteristics of memristor for 2 MHz.
Fig. 4

The voltage-current characteristics of memristor for 2 MHz.

The comparison of state of the art and this work are listed in (Tab. 1). The active and passive devices are recoded, operation frequency, emulator properties (floating or grounded) are listed in (Tab. 1).

Table 1

Comparison of the proposed memristor circuit with previous works.

ReferenceActive componentPassive deviceFrequencyMemristors type
[17]2 OP-AMPs, 1 Multiplier, 10 Transistors2 R, 1 C800 HzGrounded Memristor
[2]CBTA, 1 Multiplier2 R, 1 C100 kHzGrounded Memristor
[6]4 transistors-100 MHzGrounded Memristor
[10]4 transistors-100 kHzGrounded Memristor
[32]7 transistors1 C50 MHzGrounded Memristor
[35]VDCC, 2 transistors1 C2 MHzGrounded Memristor
[34]VDTA, single transistors-50 MHzGrounded Memristor
[28]3 OTA, 4 CCII6 R, 1 C10 kHzFloating Memristor
[5]1 MO-OTA, 1 Multiplier1 R, 1 C1 kHzFloating Memristor
[30]3 transistors1 C1 MHzFloating Memristor
[36]1 CBTA2 C1 MHzFloating Memristor
[4]1 OTA, 2 transistors1 C30 HzFloating Memristor
[3]10 transistors3 C5 HzFloating Memristor
[33]1 DDCC, 1 Multiplier2 R, 1 C1 MHzFloating Memristor
[27]4 CCII, 1 Multiplier5 R, 1 C20.2 kHzFloating Memristor

The proposed memristor can achieve up to 783 resistance levels with adaptation time equal to 500 ns between each level. The results show that the proposed memristor can be programmed up to 9.61-bit values which are higher than the recent memristors proposed in [7, 11, 13, 21, 22, 25] where authors programmed up to 121, 200, 64, 100, 30 and 24 levels, respectively. From the voltage-current characteristics of the memristor shown in (Fig. 4). Just like a biological synapse, the proposed memristor recovers the original state when the applied voltage is removed. Furthermore, the proposed memristors can be used as the weights of the synapses as well as to build the neuron for the memristor SNN as spiking adaptive sensor circuits. Moreover, the neurons built using this memristor do not need a reset after firing like the biological neurons. The proposed memristor with one transistor (1T1M) mimics synapse which can be programmed to 783 resistance levels using adapted pulses of 100 ns and controlling the transistor voltage gate to give more control of the memristor current as shown in (Fig. 5).

Fig. 5 Memristor with transistor (1T1M) architecture used to program the memristor.
Fig. 5

Memristor with transistor (1T1M) architecture used to program the memristor.

Monte-Carlo simulation of the 1T1M under temperature range (-40 °C to 85 °C) is given in (Fig. 6) to confirm workableness. The worst-case result is picked, as shown in (Fig. 7). In order to reset it the original weight of the synapse, the voltage of the gate transistor is adjusted, and the recovered result is shown in (Fig. 8).

Fig. 6 Monte-Carlo simulation of the 1T1M in the temperature range (-40 °C to 85 °C).
Fig. 6

Monte-Carlo simulation of the 1T1M in the temperature range (-40 °C to 85 °C).

Fig. 7 Worst-case of the Monte-Carlo simulation for the 1T1M.
Fig. 7

Worst-case of the Monte-Carlo simulation for the 1T1M.

Fig. 8 Recovered the worst-case of the Monte-Carlo simulation for the 1T1M.
Fig. 8

Recovered the worst-case of the Monte-Carlo simulation for the 1T1M.

The layout of the proposed floating memristor circuit (Fig. 9) in the figure which occupies 70 μm ∗ 85 μm chip area.

Fig. 9 The layout of the proposed floating memristor emulator circuit.
Fig. 9

The layout of the proposed floating memristor emulator circuit.

4 Conclusions

In this work, a compact floating memristor circuit is presented, which consists of only four MOS-transistors without requiring any external devices. By comparing it with the previous designs that needed active components like a multiplier, OP-AMP, OTA, CBTA, VDCC, VDTA, DDCC, CCII, and passive elements like capacitor and resistor. The proposed floating memristor is implemented using AMS 0.35 μm CMOS technology and simulated with cadence design tools in the temperature range (-40 °C to 85 °C) and Monte-Carlo model. The proposed floating memristor is suitable for an adaptive synapse and in an adaptive spiking neuron.

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Published Online: 2020-08-28
Published in Print: 2020-09-25

© 2020 Walter de Gruyter GmbH, Berlin/Boston

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  3. XXXIV. Messtechnisches Symposium
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  7. Ganzheitliche Kalibrierung von Gewinden auf Basis eines dreidimensionalen Ansatzes
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https://doi.org/10.1515/teme-2020-0024
Keywords for this article
Frequency sensory; Memristor; Memristor neuromorphic architectures; Adaptive synapse; Adaptive spiking neural network; Self-x properties; Machine learning; Sensor electronics system; Industry 4.0

Articles in the same Issue

  1. Frontmatter
  2. Editorial
  3. XXXIV. Messtechnisches Symposium
  4. Beiträge
  5. Detektion der Auflagestege von Flachbett-Laserschneidmaschinen mittels Nahinfrarot-Beleuchtung
  6. Lichtfeld-Tiefenschätzung für die Vermessung teilspiegelnder Oberflächen
  7. Ganzheitliche Kalibrierung von Gewinden auf Basis eines dreidimensionalen Ansatzes
  8. Analyse von 3D-CT-Aufnahmen von Spänen zur Extrahierung der Segmentspanbildungsfrequenz
  9. Resolution enhancement through nearfield-assistance in interference microscopy
  10. Fertigung polymerer optischer Phasenplatten zur Erzeugung von Ringmoden mittels direkter Laserlithografie
  11. Direct-imaging DOEs for high-NA multi-spot confocal microscopy
  12. Methoden zur Minimierung des Rauscheinflusses durch Hitzeflimmern bei einem heterodynen Laser-Doppler-Vibrometer
  13. Inverse piezoelectric material parameter characterization using a single disc-shaped specimen
  14. Klassifikation von Grübchenschäden an Zahnrädern mittels Vibrationsmessungen
  15. Incorporation of phase information for improved time-dependent instrument recognition
  16. Akustische Zeitumkehrfokussierung in Wasser mittels FPGA-basierter Plattform
  17. De-Embedding-Ansatz zur Messung nichtidealer Kapazitäten mit kommerziellen Kapazitätssensoren
  18. Low-cost Indirect Measurement Methods for Self-x Integrated Sensory Electronics for Industry 4.0
  19. Reconfigurable Wide Input Range, Fully-Differential Indirect Current-Feedback Instrumentation Amplifier with Digital Offset Calibration for Self-X Measurement Systems
  20. A Compact Four Transistor CMOS-Design of a Floating Memristor for Adaptive Spiking Neural Networks and Corresponding Self-X Sensor Electronics to Industry 4.0
  21. Monte-Carlo-Methode zur Verringerung von Messfehlern bei der Materialparameterbestimmung mit Hohlraumresonatoren
  22. Bestimmung des Anregungsspektrums für kontaktlose breitbandige Messungen der Übertragungsfunktion mit Plasmaanregung und Laser-Doppler-Vibrometrie
  23. Self-sufficient vibration sensor for high voltage lines
  24. Flexibler organischer elektrochemischer Transistor als Biosensor für Organ-on-a-Chip
  25. Erkennung und Kompensation von Vergiftung durch Siloxane auf Halbleitergassensoren im temperaturzyklischen Betrieb
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