Volume 1, Issue 4

No abstract available.

Recent ITRS lithography roadmaps show a big technology decision approaching the semiconductor industry about how to do leading edge lithography. The need is rapidly approaching for the industry to select an option for the 22-nm half pitch, but no decision has been made yet. The main options for the 22-nm half pitch are extreme ultraviolet (EUV), ArF immersion lithography with multiple patterning, and maskless lithography. For the 16-nm half pitch, directed self-assembly (DSA) is also an option. The EUV has the most industry investment and is the closest to current lithography in the way it works but still faces challenges in tool productivity and defect-free masks. The nanoimprint needs to overcome the defect, contamination, and overlay challenges before it can be applied to the semiconductor production. Maskless lithography may be used first for prototyping and small volume products where mask costs per chip produced would be very high. Double patterning could be extended to multiple pattering, but would give tremendous process complexity and exponentially rising mask costs due to the many exposures needed per level. The DSA, which only recently has emerged from the research stage, has the potential for very high resolution but represents a huge change in how critical dimensions are formed and controlled.

No abstract available.

No abstract available.

No abstract available.

Beginning with the seminal Dill papers of 1975, the aerial image has been essential for understanding the process of microlithography. From the aerial image, we can predict the performance of a given lithographic process in terms of depth of focus, exposure latitude, etc. As lithographic technologies improved, reaching smaller and smaller printed features, the sophistication of aerial image calculations has had to increase from simple incoherent imaging theory, to partial coherence, polarization effects, thin film effects at the resist, thick mask effects, and so on. This tutorial provides an overview and semihistorical development of the aerial image calculation and then provides a review of some of the various ways in which the aerial image is typically used to estimate the performance of the lithographic process.

Advances in computational lithography over the last 10 years have been instrumental to the continued scaling of semiconductor devices. Competitive scaling requires two types of complementary models: fast predictive empirical models that can be used for pattern correction and verification; rigorous physical models that can be used to identify key physical effects that must be considered to ensure pattern fidelity, but are too resource intensive to use for full chip applications. Today, all computational lithography efforts such as the optical proximity correction (OPC) and the optical rules check (ORC) depend on the ability to predictively model the lithography and metrology processes. We discuss some of the current modeling practices in optics, mask, resist and etching, leading to the “Holy Grail” of predictively modeling entire patterning process which we call “virtual fab”. Extreme ultraviolet (EUV) modeling is discussed due to its potential to extend optical lithography scaling for future nodes. Modeling of novel technologies such as Diblock Copolymer patterning is also discussed to demonstrate new opportunities for continued scaling. Complexity of the “virtual fab” approach is extremely high as there are multiple dimensions in this approach. The need to overcome this complexity, by reducing the number of dimensions of the problem, is evident. Lastly, the ability to leverage lithography modeling in design co-optimization is an important element of semiconductor device scaling.

This paper reports on the current status for the key infrastructures of the extreme ultraviolet lithography (EUVL) for sub-20-nm half pitch (hp) generation. More specifically, the inspection technologies for EUV mask and resist-related technologies will be dedicatedly discussed. First, the actinic blank inspector is strongly required especially for sub-20-nm hp generation. The basic configuration of the prototyping tool will be presented. Second, the basic configuration of the newly developing patterned mask inspector (PMI) consisting of the projection-type optics for the electron beam (EB) will be presented. The primary challenge for the EUV resist is the concurrent improvements of resolution, line width roughness, sensitivity, and outgas. The basic performance of the EUV resist and preliminary validation of the outgas qualification for sub-20-nm hp will be presented.

Extreme ultraviolet (EUV) lithography has emerged as the preferred choice for high-volume manufacturing, now that immersion ArF reaches its limits. Light source power is a key driver to achieve the throughput required for successful adoption of extreme ultraviolet lithography (EUVL). Cymer has developed a laser-produced plasma source based on a high-power CO 2 drive laser exciting tin targets to emit 13.5 nm light. Five sources are currently installed at chipmaker fabs and are being used for process development. The power output of the fielded source configuration is currently 20 W, lower than required for manufacturing introduction. The technology for scaling up power is under development, focusing on increasing the conversion efficiency and collection efficiency of the source. Increasing drive laser power to 17 kW has allowed the demonstration of EUV power of nearly 50 W, with paths identified for further scaling to 100 W. An additional focus on product reliability has driven the availability up to 70%, primarily through extending the collector mirror lifetime.

Photomasks carry the structured information of the chip designs printed with lithography scanners onto wafers. These structures, for the most modern technologies, are enlarged by a factor of 4 with respect to the final circuit design, and 20–60 of these photomasks are needed for the production of a single completed chip used, for example, in computers or cell phones. Lately, designs have been reported to be on the drawing board with close to 100 of these layers. Each of these photomasks will be reproduced onto the wafer several hundred times and typically 5000–50 000 wafers will be produced with each of them. Hence, the photomasks need to be absolutely defect-free to avoid any fatal electrical shortcut in the design or drastic performance degradation. One well-known method in the semiconductor industry is to analyze the aerial image of the photomask in a dedicated tool referred to as Aerial Imaging Measurement System, which emulates the behavior of the respective lithography scanner used for the imaging of the mask. High-end lithography scanners use light with a wavelength of 193 nm and high numerical apertures (NAs) of 1.35 utilizing a water film between the last lens and the resist to be illuminated (immersion scanners). Complex illumination shapes enable the imaging of structures well below the wavelength used. Future lithography scanners will work at a wavelength of 13.5 nm [extreme ultraviolet (EUV)] and require the optical system to work with mirrors in vacuum instead of the classical lenses used in current systems. The exact behavior of these systems is emulated by the Aerial Image Measurement System (AIMS™; a Trademark of Carl Zeiss). With these systems, any position of the photomask can be imaged under the same illumination condition used by the scanners, and hence, a prediction of the printing behavior of any structure can be derived. This system is used by mask manufacturers in their process flow to review critical defects or verify defect repair success. In this paper, we give a short introduction into the lithography roadmap driving the development cycles of the AIMS systems focusing primarily on the complexity of the structures to be reviewed. Second, we describe the basic principle of the AIMS technology and how it is used. The last section is dedicated to the development of the latest generation of the AIMS for EUV, which is cofinanced by several semiconductor companies in order to close a major gap in the mask manufacturing infrastructure and the challenges to be met.

Mask manufacturers will be impacted by two significant technology requirements at 22 nm and below: the first is the more extensive use of resolution enhancement technologies (RET), such as aggressive optical proximity correction (OPC), inverse lithography technology (ILT), and source mask optimization (SMO); the second is the extreme ultraviolet (EUV) technology. Both will create difficulties for mask inspection, defect disposition, metrology, review, and repair. For example, the use of ILT and SMO significantly increases mask complexity, making mask defect disposition more challenging than ever. The EUV actinic inspection and AIMS™ will not be available for at least a few years, which make the EUV defect inspection and disposition more difficult, particularly regarding multilayer defects. Computational metrology and inspection (CMI), which has broad applications in mask inspection, metrology, review, and repair, has become essential to fill this technology gap. In this paper, several such CMI applications are presented and discussed.

The k1 factor continues to be driven downward, in order to enable the 22-nm feature generation and beyond. Such a low k1 factor tends to lead to extremely small process windows. For such demanding imaging challenges, it is not only necessary for each unit, contributing to the imaging system, to be driven to its ultimate performance capability, but also that active techniques that can expand the process window and the robustness of the imaging against various kinds of imaging parameters be implemented. One such technique is source and mask optimization (SMO). In this paper, we study the effect of SMO. Furthermore, we discuss how to realize the SMO solution in the imaging system setup on the scanner. The setup process includes freeform pupilgram generation (source intensity distribution on the pupil) and pupilgram adjustment.

Modern phase shifting interferometers enable the manufacture of optical systems that drive the global economy. Semiconductor chips, solid-state cameras, cell phone cameras, infrared imaging systems, space-based satellite imaging, and DVD and Blu-Ray disks are all enabled by phase-shifting interferometers. Theoretical treatments of data analysis and instrument design advance the technology but often are not helpful toward the practical use of interferometers. An understanding of the parameters that drive the system performance is critical to produce useful results. Any interferometer will produce a data map and results; this paper, in three parts, reviews some of the key issues to minimize error sources in that data and provide a valid measurement.