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How to make lithography patterns print: the role of OPC and pattern layout

  • Peter De Bisschop

    Peter De Bisschop obtained a PhD in Atomic Physics in 1984 and has been at IMEC since 1986. Until 1995, he worked in the Materials Analysis group and, since then, he has worked in the Advanced Lithography Department. Among the topics he has worked on are stepper/scanner control, monitoring and qualification, lens aberrations, stray light, laser-bandwidth effects, CDU, 157-nm hard pellicles, 193i air bubble defects, M3D effects, and rigorous lithographic simulations. For the past 10 years, his focus has been on proximity-related topics, OPC modeling and verification, contour metrology, as well as DTCO and logic cell layout, and EUV stochastic effects.

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Published/Copyright: May 20, 2015
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Advanced Optical Technologies
From the journal Advanced Optical Technologies Volume 4 Issue 4

Abstract

This paper will review some of the methods that have been devised to bring lithography-generated patterns as close to the desired target patterns as possible, while making them also robust against inevitable deviations from the ideal conditions during the printing process. Optical proximity correction (OPC) is the first step in this process. Various ways have been developed for efficient creation of accurate process window aware OPC models. Also, the use of the actual OPC step, to transform the target patterns into actual lithography mask patterns has seen significant progress. A computational verification step then checks whether the predicted pattern shapes meet the quality requirements and identifies any residual failures or weak patterns (‘hotspots’). Once the mask is available, a second verification step, now looking at patterns on printed wafers, is performed to make sure that all critical patterns print to within the requested tolerances. Each of the steps in this flow can – and usually does – lead to corrective iterations to one of the previous steps. As the task of ensuring sufficient process margin is gradually becoming more difficult, with the ever decreasing pattern sizes, constraints are being increasingly defined on the type of patterns that can be allowed in the target layout itself (design restrictions), leading to a tendency toward more regular designs, an evolution that needs to be facilitated by the patterning technology and materials used. So the problem of ensuring good printability now also involves both layout and technology, and we will look into this aspect of the optimization problem as well.

Keywords: DTCO; geometrical layout restrictions; OPC; optical lithography; unidirectional layouts
Corresponding author: Peter De Bisschop, Advanced Lithography Department, IMEC, Kapeldreef 75, B-3001 Leuven, Belgium, e-mail:

About the author

Peter De Bisschop

Peter De Bisschop obtained a PhD in Atomic Physics in 1984 and has been at IMEC since 1986. Until 1995, he worked in the Materials Analysis group and, since then, he has worked in the Advanced Lithography Department. Among the topics he has worked on are stepper/scanner control, monitoring and qualification, lens aberrations, stray light, laser-bandwidth effects, CDU, 157-nm hard pellicles, 193i air bubble defects, M3D effects, and rigorous lithographic simulations. For the past 10 years, his focus has been on proximity-related topics, OPC modeling and verification, contour metrology, as well as DTCO and logic cell layout, and EUV stochastic effects.

Acknowledgments

Many thanks to the following people: Jeroen Van de Kerkhove, Julien Mailfert, Staf Verhaegen, Darko Trivkovic, Werner Gillijns, Monique Ercken, Geert Vandenberghe, Patrick Wong, Vicky Philipsen, Alessandro Vaglio Pret, Mustafa Badaroglu, Julien Ryckaert, Karim Mercha, Jürgen Bömmels, Naoto Horiguchi, David Rio, Bart Laenens, Hua-yu Liu, Mu Feng, Germain Fenger, John Sturtevant, Kostas Adam, James Word, Andres Torres, Weimin Gao, Kevin Lucas, Ulrich Klöstermann, Chris Cork, Gerry Luk-Pat, Lena Zavyalova, Daisuke Fuchimoto, Hiroyuki Shindo, Daisuke Hibino, Doni Parnell, Grozdan Grozev, Shinji Tarutani, Mike Smayling, and Andreas Erdmann.

Appendix: summary of the main abbreviations used

DDM, Domain-Decomposition Method; DR, Design Rule; DRC, Design-Rule Check; DTCO, Design-Technology co-Optimization; EDA, Electronic Design Automation; EOL/EOT, End-of-Line/End-of-Trench; EPE, Edge-Placement Error; FE, Focus-Exposure; ILT, Inverse Lithography Technology; IPS, Image Parameter Space; ISP, In-Spec Percentage; LI, Local Interconnect; M3D, Mask 3D (or topography); M0, Metal0; M1, Metal1; MRC, Mask-Rule Check; MTT, Mean-to-Target; NTD, Negative-Tone Development; N20, 20 nm (Logic) node; OPC, Optical Proximity Correction; PTD, Positive-Tone Development; PV, Process Variation; PW, Process Window; R3D, Resist 3D (or resist profile); SADP, Self-Aligned Double Patterning; SRAF, Sub-Resolution Assist Feature; STI, Shallow-Trench Isolation; VB, Variability Band.

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Received: 2015-3-15
Accepted: 2015-4-14
Published Online: 2015-5-20
Published in Print: 2015-8-1

©2015 THOSS Media & De Gruyter

Articles in the same Issue

  1. Cover and Frontmatter
  2. Views
  3. ITRS lithography roadmap: 2015 challenges
  4. Community
  5. EOS NEWS: Report from the World of Photonics Congress 2015
  6. Conference Notes
  7. Conference Calendar
  8. Topical Issue: Optical Lithography
  9. Editorial
  10. Introduction to the special issue on optical lithography
  11. Review Articles
  12. How to make lithography patterns print: the role of OPC and pattern layout
  13. Exposure tool control for advanced semiconductor lithography
  14. Performance of 100-W HVM LPP-EUV source
  15. Resist material options for extreme ultraviolet lithography
  16. Development of element technologies for EUVL
  17. Research Articles
  18. Focus tolerance influenced by source size in Talbot lithography
  19. Flat-field anastigmatic mirror objective for high-magnification extreme ultraviolet microscopy
https://doi.org/10.1515/aot-2015-0023
Keywords for this article
DTCO; geometrical layout restrictions; OPC; optical lithography; unidirectional layouts

Articles in the same Issue

  1. Cover and Frontmatter
  2. Views
  3. ITRS lithography roadmap: 2015 challenges
  4. Community
  5. EOS NEWS: Report from the World of Photonics Congress 2015
  6. Conference Notes
  7. Conference Calendar
  8. Topical Issue: Optical Lithography
  9. Editorial
  10. Introduction to the special issue on optical lithography
  11. Review Articles
  12. How to make lithography patterns print: the role of OPC and pattern layout
  13. Exposure tool control for advanced semiconductor lithography
  14. Performance of 100-W HVM LPP-EUV source
  15. Resist material options for extreme ultraviolet lithography
  16. Development of element technologies for EUVL
  17. Research Articles
  18. Focus tolerance influenced by source size in Talbot lithography
  19. Flat-field anastigmatic mirror objective for high-magnification extreme ultraviolet microscopy
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