Volume 56, Issue 4 - Special Issue dedicated to Bernd Becker on the occasion of his 60th birthday: Testing Integrated Circuits / Rolf Drechsler

In this paper we provide experimental evidence that digital VLSI circuit designs using an earlier proposed DFT method called segmented scan may be testable using fewer tests than needed for unsegmented scan versions of the same designs. Results on ISCAS 89 benchmark circuits show that the test set sizes for detecting stuck-at faults in segmented scan designs may be lower than the lower bounds on test set sizes for unsegmented scan versions. Thus, segmented scan design may be a way to achieve minimal test set sizes for digital VLSI circuits.

Each chip is subjected to a post-production test after fabrication. A set of test patterns is applied to filter out defective devices. The size of this test set is an important issue. Generally, large test sets increase the test costs. Therefore, test compaction techniques are applied to obtain a compact test set. The effectiveness of these technique is significantly influenced by fault ordering. This paper describes how information about hard-to-detect faults can be extracted from an untestable identification phase and be used to develop a fault ordering technique which is able to reduce the pattern counts of highly compacted test sets generated by a SAT-based dynamic test compaction approach.

To cope with the problems of technology scaling, a robust design has become desirable. Self-checking circuits combined with rollback or repair strategies can provide a low cost solution for many applications. However, standard synthesis procedures may violate design constraints or lead to sub-optimal designs. The SAT-based strategies for the verification and synthesis of self-checking circuits presented in this paper can provide efficient solutions.

This paper addresses the detection improvement of Gate Oxide Short defect using a delay test strategy. To achieve this objective, the concept of detectability interval is first introduced in the context of detection of short defects using Boolean test technique. Then this paradigm is extended to the detection of Gate Oxide Short defects using delay testing. Finally, it is shown that it is possible to significantly improve the detection of this kind of defect.

Stochastic computing is an old and unconventional computing technique that is finding promising new applications in image processing and the handling of complex error-correcting codes. Stochastic circuits offer an alternative to conventional digital circuits because of their extremely small size and inherent noise tolerance. They are also well-suited to meeting the requirements of emerging nanoscale technologies where non-deterministic behavior due to manufacturing defects and soft errors cannot be ignored. Error analysis of stochastic circuits, however, has received little attention and remains a largely open problem, especially when multiple errors affecting both the data sources and the stochastic circuits can occur in the course of a computation. This paper attempts to analyze stochastic circuits under various error conditions, and to compare their behavior to that of conventional circuits under similar error conditions. We use probabilistic transfer matrices for this analysis, complemented by circuit simulation. Our results indicate that stochastic circuits provide significantly better error tolerance under severe error conditions.

Hardware security is a relatively new scientific discipline which focuses on adversarial threats to hardware components of complex systems and infrastructures, including manipulation, unauthorized access to confidential data, and intellectual property theft. State-of-the-art test methods can contribute to detection and elimination of security threats but also may introduce new vulnerabilities. This article will explain this dichotomy and outline current research challenges.