Skip to main content
Article
Licensed
Unlicensed Requires Authentication

SAT-based ATPG beyond stuck-at fault testing

Applications to fault tolerance

  • Sybille Hellebrand chairs the Computer Engineering Group (DATE) at the Institute of Electrical Engineering and Information Technology at the University of Paderborn. Her research interests are in the area of test, diagnosis, and fault tolerance of integrated circuits and systems.

    Computer Engineering Group, EIM-E, University of Paderborn, Warburger Str. 100, 33098 Paderborn, Germany

     EMAIL logo     and

    Hans-Joachim Wunderlich is Director of the Institute of Computer Architecture and Computer Engineering (ITI) at the University of Stuttgart. He has authored and co-authored more than 200 publications in the area of test, reliability, and fault tolerance.

    Institut of Computer Engineering (ITI),University of Stuttgart, Pfaffenwaldring 47, 70569 Stuttgart, Germany
Published/Copyright: July 21, 2014
it - Information Technology
From the journal it - Information Technology Volume 56 Issue 4

Abstract

To cope with the problems of technology scaling, a robust design has become desirable. Self-checking circuits combined with rollback or repair strategies can provide a low cost solution for many applications. However, standard synthesis procedures may violate design constraints or lead to sub-optimal designs. The SAT-based strategies for the verification and synthesis of self-checking circuits presented in this paper can provide efficient solutions.

Keywords: ACM CCS→Hardware→Hardware test; SAT-based ATPG; Fault Tolerance; Self-Checking Circuits; Synthesis

About the authors

Sybille Hellebrand

Sybille Hellebrand chairs the Computer Engineering Group (DATE) at the Institute of Electrical Engineering and Information Technology at the University of Paderborn. Her research interests are in the area of test, diagnosis, and fault tolerance of integrated circuits and systems.

Computer Engineering Group, EIM-E, University of Paderborn, Warburger Str. 100, 33098 Paderborn, Germany

Hans-Joachim Wunderlich

Hans-Joachim Wunderlich is Director of the Institute of Computer Architecture and Computer Engineering (ITI) at the University of Stuttgart. He has authored and co-authored more than 200 publications in the area of test, reliability, and fault tolerance.

Institut of Computer Engineering (ITI),University of Stuttgart, Pfaffenwaldring 47, 70569 Stuttgart, Germany

Received: 2013-12-08
Accepted: 2014-02-27
Published Online: 2014-07-21
Published in Print: 2014-08-28

©2014 Walter de Gruyter Berlin/Boston

Articles in the same Issue

  1. Frontmatter
  2. Editorial
  3. Preface
  4. Editorial
  5. Testing integrated circuits
  6. Special Issue
  7. On achieving minimal size test sets for scan designs
  8. An effective fault ordering heuristic for SAT-based dynamic test compaction techniques
  9. SAT-based ATPG beyond stuck-at fault testing
  10. Testing for gate oxide short defects using the detectability interval paradigm
  11. Behavior of stochastic circuits under severe error conditions
  12. Hardware security and test: Friends or enemies?
https://doi.org/10.1515/itit-2013-1043
Keywords for this article
ACM CCS→Hardware→Hardware test; SAT-based ATPG; Fault Tolerance; Self-Checking Circuits; Synthesis

Articles in the same Issue

  1. Frontmatter
  2. Editorial
  3. Preface
  4. Editorial
  5. Testing integrated circuits
  6. Special Issue
  7. On achieving minimal size test sets for scan designs
  8. An effective fault ordering heuristic for SAT-based dynamic test compaction techniques
  9. SAT-based ATPG beyond stuck-at fault testing
  10. Testing for gate oxide short defects using the detectability interval paradigm
  11. Behavior of stochastic circuits under severe error conditions
  12. Hardware security and test: Friends or enemies?
Downloaded on 17.4.2026 from https://www.degruyterbrill.com/document/doi/10.1515/itit-2013-1043/html
Scroll to top button