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An effective fault ordering heuristic for SAT-based dynamic test compaction techniques
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Veröffentlicht/Copyright:
21. Juli 2014
Abstract
Each chip is subjected to a post-production test after fabrication. A set of test patterns is applied to filter out defective devices. The size of this test set is an important issue. Generally, large test sets increase the test costs. Therefore, test compaction techniques are applied to obtain a compact test set. The effectiveness of these technique is significantly influenced by fault ordering. This paper describes how information about hard-to-detect faults can be extracted from an untestable identification phase and be used to develop a fault ordering technique which is able to reduce the pattern counts of highly compacted test sets generated by a SAT-based dynamic test compaction approach.
Keywords: ACM CCS→Hardware→Hardware test→Test-pattern generation and fault simulation; Test; Fault ordering; Compaction; Heuristic; Circuit
Received: 2013-11-13
Accepted: 2014-02-26
Published Online: 2014-07-21
Published in Print: 2014-08-28
©2014 Walter de Gruyter Berlin/Boston
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Artikel in diesem Heft
- Frontmatter
- Editorial
- Preface
- Editorial
- Testing integrated circuits
- Special Issue
- On achieving minimal size test sets for scan designs
- An effective fault ordering heuristic for SAT-based dynamic test compaction techniques
- SAT-based ATPG beyond stuck-at fault testing
- Testing for gate oxide short defects using the detectability interval paradigm
- Behavior of stochastic circuits under severe error conditions
- Hardware security and test: Friends or enemies?
Schlagwörter für diesen Artikel
ACM CCS→Hardware→Hardware test→Test-pattern generation and fault simulation;
Test;
Fault ordering;
Compaction;
Heuristic;
Circuit
Artikel in diesem Heft
- Frontmatter
- Editorial
- Preface
- Editorial
- Testing integrated circuits
- Special Issue
- On achieving minimal size test sets for scan designs
- An effective fault ordering heuristic for SAT-based dynamic test compaction techniques
- SAT-based ATPG beyond stuck-at fault testing
- Testing for gate oxide short defects using the detectability interval paradigm
- Behavior of stochastic circuits under severe error conditions
- Hardware security and test: Friends or enemies?
