An Optimized Hardware Architecture of 4×4 Intra Prediction for HEVC Standard
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M. Kammoun
Abstract
The High Efficiency Video Coding (HEVC) is a proposal of new video coding standard that will be used for a wide range of applications like ULTRA HD and 3D applications. The Moving Picture Expert Group (MPEG) and the Video Coding Expert Group (VCEG) have established a Joint Collaborative Team on Video Coding (JCT-VC) to develop the HEVC standard which is expected to provide a significant improvement in data transmission and streaming efficiency compared to H.264/AVC (Advanced Video Coding). In this proposal standard, various modules of coding are defined. Among the most complex is the module of the intra prediction. The HEVC defines 35 modes of intra prediction for 8×8, 16×16, 32×32, 3 modes for 64×64 and 17 modes for 4×4 while the H.264 uses 9 modes for intra 4×4 and 4 modes for intra 16×16. In this paper, we propose an efficient uniform architecture for all of the 4×4 intra directional modes. This architecture offers an important gain in case of treatment time compared to the literature. Our proposed architecture is designed using VHDL language and implemented with FPGA and TSMC 0.18 μm CMOS technologies.
Abstract
The High Efficiency Video Coding (HEVC) is a proposal of new video coding standard that will be used for a wide range of applications like ULTRA HD and 3D applications. The Moving Picture Expert Group (MPEG) and the Video Coding Expert Group (VCEG) have established a Joint Collaborative Team on Video Coding (JCT-VC) to develop the HEVC standard which is expected to provide a significant improvement in data transmission and streaming efficiency compared to H.264/AVC (Advanced Video Coding). In this proposal standard, various modules of coding are defined. Among the most complex is the module of the intra prediction. The HEVC defines 35 modes of intra prediction for 8×8, 16×16, 32×32, 3 modes for 64×64 and 17 modes for 4×4 while the H.264 uses 9 modes for intra 4×4 and 4 modes for intra 16×16. In this paper, we propose an efficient uniform architecture for all of the 4×4 intra directional modes. This architecture offers an important gain in case of treatment time compared to the literature. Our proposed architecture is designed using VHDL language and implemented with FPGA and TSMC 0.18 μm CMOS technologies.
Kapitel in diesem Buch
- Frontmatter I
- Preface of the Editors V
- Advances in Systems, Signals and Devices VII
- Editorial Board Members VIII
- Advances in Systems, Signals and Devices XI
- Contents XIII
- New Proposed Adaptive Beamforming Algorithms Based on Merging CGM and NLMS methods 1
- Efficient Hardware Architecture of DCT Cordic based Loeffler Compression Algorithm for Wireless Endoscopic Capsule 23
- Exploring the Physical Characteristics of an On-chip Router for its Integration in a 3D-mesh NoC 37
- Compact High Speed Hardware for SHA-2 on FPGA 47
- An Extensible Platform for Smart Home Services 61
- Fuzzy-Based Gang Scheduling Approach for Multiprocessor Systems 81
- A Robust Multiple Watermarking Scheme Based on the DWT 97
- Retinal Identification System based on Optical Disc Ring Extraction and New Local SIFT-RUK Descriptor 113
- An Optimized Hardware Architecture of 4×4 Intra Prediction for HEVC Standard 127
- Arabic Continuous Speech Recognition Based on Hybrid SVM/HMM Model 145
- Enhancing the Odd Peaks Detection in OFDM Systems Using Wavelet Transforms 161
- Methodology for Analysis of Direct Sampling Receiver Architectures from Signal Processing and System Perspective 175
- A Hybrid PAPR Reduction Scheme for OFDM Using SLM with Clipping at the Transmitter, and Sparse Reconstruction at the Receiver 197
- Mobile Workflow Management System Architecture Taking into Account Relevant Security Requirements 217
Kapitel in diesem Buch
- Frontmatter I
- Preface of the Editors V
- Advances in Systems, Signals and Devices VII
- Editorial Board Members VIII
- Advances in Systems, Signals and Devices XI
- Contents XIII
- New Proposed Adaptive Beamforming Algorithms Based on Merging CGM and NLMS methods 1
- Efficient Hardware Architecture of DCT Cordic based Loeffler Compression Algorithm for Wireless Endoscopic Capsule 23
- Exploring the Physical Characteristics of an On-chip Router for its Integration in a 3D-mesh NoC 37
- Compact High Speed Hardware for SHA-2 on FPGA 47
- An Extensible Platform for Smart Home Services 61
- Fuzzy-Based Gang Scheduling Approach for Multiprocessor Systems 81
- A Robust Multiple Watermarking Scheme Based on the DWT 97
- Retinal Identification System based on Optical Disc Ring Extraction and New Local SIFT-RUK Descriptor 113
- An Optimized Hardware Architecture of 4×4 Intra Prediction for HEVC Standard 127
- Arabic Continuous Speech Recognition Based on Hybrid SVM/HMM Model 145
- Enhancing the Odd Peaks Detection in OFDM Systems Using Wavelet Transforms 161
- Methodology for Analysis of Direct Sampling Receiver Architectures from Signal Processing and System Perspective 175
- A Hybrid PAPR Reduction Scheme for OFDM Using SLM with Clipping at the Transmitter, and Sparse Reconstruction at the Receiver 197
- Mobile Workflow Management System Architecture Taking into Account Relevant Security Requirements 217
