Compact High Speed Hardware for SHA-2 on FPGA
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M. Anane
Abstract
Hash functions play an important role in modern cryptography. They are widely used to provide services of data integrity and authentication. Hash algorithms are based on performing a number of complex operations on the input data that require a significant amount of computing resources especially when the input data are huge.Thus, hardware implementation is far more suitable, for security and performances execution issues, compared to the corresponding software implementations. Hash functions perform internal operations in an iterative fashion, which open the possibility of exploring several implementation strategies. In this paper, we are concerned by optimizing the hardware implementation of the SHA-256 algorithm on Virtex-5 of Xilinx FPGA. Our main contribution is to design a compact SHA-256 core and to speed-up its critical paths which are respectively seven and six words addition. The CS (Carry Save) representation is advantageously used to overcome the carry propagation, until the last addition. Special efforts were made to design, at the LUT level, the two components (compressors 7:2 and 6:2) which are the key features of our design; their delay is data path independent and equivalent to the delay of two LUT6. The resulting architecture is compact and operates at 170MHzwith a throughput of 1.36 Gbps.
Abstract
Hash functions play an important role in modern cryptography. They are widely used to provide services of data integrity and authentication. Hash algorithms are based on performing a number of complex operations on the input data that require a significant amount of computing resources especially when the input data are huge.Thus, hardware implementation is far more suitable, for security and performances execution issues, compared to the corresponding software implementations. Hash functions perform internal operations in an iterative fashion, which open the possibility of exploring several implementation strategies. In this paper, we are concerned by optimizing the hardware implementation of the SHA-256 algorithm on Virtex-5 of Xilinx FPGA. Our main contribution is to design a compact SHA-256 core and to speed-up its critical paths which are respectively seven and six words addition. The CS (Carry Save) representation is advantageously used to overcome the carry propagation, until the last addition. Special efforts were made to design, at the LUT level, the two components (compressors 7:2 and 6:2) which are the key features of our design; their delay is data path independent and equivalent to the delay of two LUT6. The resulting architecture is compact and operates at 170MHzwith a throughput of 1.36 Gbps.
Kapitel in diesem Buch
- Frontmatter I
- Preface of the Editors V
- Advances in Systems, Signals and Devices VII
- Editorial Board Members VIII
- Advances in Systems, Signals and Devices XI
- Contents XIII
- New Proposed Adaptive Beamforming Algorithms Based on Merging CGM and NLMS methods 1
- Efficient Hardware Architecture of DCT Cordic based Loeffler Compression Algorithm for Wireless Endoscopic Capsule 23
- Exploring the Physical Characteristics of an On-chip Router for its Integration in a 3D-mesh NoC 37
- Compact High Speed Hardware for SHA-2 on FPGA 47
- An Extensible Platform for Smart Home Services 61
- Fuzzy-Based Gang Scheduling Approach for Multiprocessor Systems 81
- A Robust Multiple Watermarking Scheme Based on the DWT 97
- Retinal Identification System based on Optical Disc Ring Extraction and New Local SIFT-RUK Descriptor 113
- An Optimized Hardware Architecture of 4×4 Intra Prediction for HEVC Standard 127
- Arabic Continuous Speech Recognition Based on Hybrid SVM/HMM Model 145
- Enhancing the Odd Peaks Detection in OFDM Systems Using Wavelet Transforms 161
- Methodology for Analysis of Direct Sampling Receiver Architectures from Signal Processing and System Perspective 175
- A Hybrid PAPR Reduction Scheme for OFDM Using SLM with Clipping at the Transmitter, and Sparse Reconstruction at the Receiver 197
- Mobile Workflow Management System Architecture Taking into Account Relevant Security Requirements 217
Kapitel in diesem Buch
- Frontmatter I
- Preface of the Editors V
- Advances in Systems, Signals and Devices VII
- Editorial Board Members VIII
- Advances in Systems, Signals and Devices XI
- Contents XIII
- New Proposed Adaptive Beamforming Algorithms Based on Merging CGM and NLMS methods 1
- Efficient Hardware Architecture of DCT Cordic based Loeffler Compression Algorithm for Wireless Endoscopic Capsule 23
- Exploring the Physical Characteristics of an On-chip Router for its Integration in a 3D-mesh NoC 37
- Compact High Speed Hardware for SHA-2 on FPGA 47
- An Extensible Platform for Smart Home Services 61
- Fuzzy-Based Gang Scheduling Approach for Multiprocessor Systems 81
- A Robust Multiple Watermarking Scheme Based on the DWT 97
- Retinal Identification System based on Optical Disc Ring Extraction and New Local SIFT-RUK Descriptor 113
- An Optimized Hardware Architecture of 4×4 Intra Prediction for HEVC Standard 127
- Arabic Continuous Speech Recognition Based on Hybrid SVM/HMM Model 145
- Enhancing the Odd Peaks Detection in OFDM Systems Using Wavelet Transforms 161
- Methodology for Analysis of Direct Sampling Receiver Architectures from Signal Processing and System Perspective 175
- A Hybrid PAPR Reduction Scheme for OFDM Using SLM with Clipping at the Transmitter, and Sparse Reconstruction at the Receiver 197
- Mobile Workflow Management System Architecture Taking into Account Relevant Security Requirements 217
