A review of nanoimprint lithography for high-volume semiconductor device manufacturing
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Douglas J. Resnick
und
Jin Choi
Abstract
Imprint lithography has been shown to be a promising technique for the replication of nanoscale features. Jet and flash imprint lithography (J-FIL) [jet and flash imprint lithography and J-FIL are trademarks of Molecular Imprints, Inc.] involves the field-by-field deposition and exposure of a low-viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid, which then quickly flows into the relief patterns in the mask by capillary action. After this filling step, the resist is cross-linked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are many criteria that determine whether a particular technology is ready for wafer manufacturing. Included on the list are overlay, throughput, and defectivity. The most demanding devices now require an overlay of better than 4 nm, 3σ. Throughput for an imprint tool is generally targeted at 80 wafers/h. Defectivity and mask life play a significant role relative to meeting the cost of ownership (CoO) requirements in the production of semiconductor devices. The purpose of this paper is to report the status of throughput and defectivity work and to describe the progress made in addressing overlay for advanced devices. To address high-order corrections, a high-order distortion correction (HODC) system is introduced. The combination of applying magnification actuation to the mask and temperature correction to the wafer is described in detail. Examples are presented for the correction of K7, K11, and K17 distortions as well as distortions on actual device wafers.
Acknowledgments
The authors would like to thank Takabayashi-san, Nakayama-san, and Zhengmao Ye along with the fine work of many other engineers at both Canon and Canon Nanotechnologies. We are also grateful to Dai Nippon Printing for providing the imprint masks used in these studies.
References
[1] S. Y. Chou, P. R. Kraus and P. J. Renstrom, J. Vac. Sci. Technol. B 14, 4129 (1996).10.1116/1.588605Suche in Google Scholar
[2] T. K. Widden, D. K. Ferry, M. N. Kozicki, E. Kim, A. Kumar, et al., Nanotechnology 7, 447 (1996).10.1088/0957-4484/7/4/027Suche in Google Scholar
[3] H. Schift and A. Kristensen, in ‘Handbook of Nanotechnology’, Ed. by B. Bhushan, 3rd ed. (Springer-Verlag, Berlin/Heidelberg, Germany, 2010) pp. 271–312.10.1007/978-3-642-02525-9_9Suche in Google Scholar
[4] M. Otto, M. Bender, B. Hadam, B. Spangenberg and H. Kurz, Microelectron. Eng. 57–58, 361 (2001).10.1016/S0167-9317(01)00536-6Suche in Google Scholar
[5] M. Colburn, S. Johnson, S. Damle, T. Bailey, B. Choi, et al., Proc. SPIE 3676, 379 (1999).Suche in Google Scholar
[6] M. Colburn, I. Suez, B. J. Choi, M. Meissl, T. Bailey, et al., J. Vac. Sci. Technol. B 19, 2685 (2001).10.1116/1.1420199Suche in Google Scholar
[7] M. Hatano, K. Kobayashi, H. Kashiwagi, H. Tokue, T. Kono, et al., Proc. SPIE 9777, Altern. Lithogr. Technol. VIII, 97770B (2016).Suche in Google Scholar
[8] M. Colburn, T. Bailey, B. J. Choi, J. G. Ekerdt and S. V. Sreenivasan, Solid State Technol. 44, 67 (2001).Suche in Google Scholar
[9] T. C. Bailey, D. J. Resnick, D. Mancini, K. J. Nordquist, W. J. Dauksher, et al., Microelectron. Eng. 61–62, 461 (2002).10.1016/S0167-9317(02)00462-8Suche in Google Scholar
[10] S. V. Sreenivasan, P. Schumaker, B. Mokaberi-Nezhad, J. Choi, J. Perez, et al., Presented at the SPIE Advanced Lithography Symposium, Conference 7271 (2009).Suche in Google Scholar
[11] K. Selenidis, J. Maltabes, I. McMackin, J. Perez, W. Martin, et al., Proc. SPIE 6730, 67300F-1 (2007).10.1117/12.747565Suche in Google Scholar
[12] I. McMackin, J. Choi, P. Schumaker, V. Nguyen, F. Xu, et al., Proc. SPIE 5374, 222 (2004).10.1117/12.538733Suche in Google Scholar
[13] T. Higashiki, T. Nakasugi and I. Yoneda, Proc. SPIE 7970, Altern. Lithogr. Technol. III, 797003 (2011).10.1117/12.882940Suche in Google Scholar
[14] Z. Ye, K. Luo, J. W. Irving, X. Lu, W. Zhang, et al., Proc. SPIE 8680, Altern. Lithogr. Technol. V, 86800C (2013).10.1117/12.2013694Suche in Google Scholar
[15] H. Takeishi and S. V. Sreenivasan, Proc. SPIE 9423, Altern. Lithogr. Technol. VII, 94230C (2015)10.1117/12.2087017Suche in Google Scholar
[16] W. Zhang, B. Fletcher, E. Thompson, W. Liu, T. Stachowiak, et al., Proc. SPIE 9777, Altern. Lithogr. Technol. VIII, 97770A (2016).10.1117/12.2219161Suche in Google Scholar
[17] P. Xu, Y. Chen, Y. Chen, L. Miao, S. Sun, et al., Proc. SPIE 7973 79731Q-1 (2011).10.1117/12.881547Suche in Google Scholar
[18] K. Emoto, F. Sakai, C. Sato, Y. Takabayashi, H. Nakano, et al., Proc. SPIE 9777, Altern. Lithogr. Technol. VIII, 97770A (2016).10.1117/12.2219036Suche in Google Scholar
[19] H. Hiura, Y. Takabayashi, T. Takashima, K. Emoto, J. Choi, et al., Proc. SPIE 10032, 32nd Eur. Mask Lithogr. Conf. 100320E (2016).10.1117/12.2248363Suche in Google Scholar
[20] T. Nakayama et al., Presented at the SPIE Advanced Lithography Symposium, February 28, 2017.Suche in Google Scholar
[21] B. J. Choi, K. Nordquist, A. Cherala, L. Casoose and K. Gehoski, Microelectron. Eng. 78–79, 633 (2005).10.1016/j.mee.2004.12.097Suche in Google Scholar
[22] T. Higashiki, Presented at the SPIE Advanced Lithography Symposium, February 27, 2017.Suche in Google Scholar
©2017 THOSS Media & De Gruyter, Berlin/Boston
Artikel in diesem Heft
- Cover and Frontmatter
- Views
- Patterning roadmap: 2017 prospects
- Community
- Conference Notes
- News from the European Optical Society (EOS)
- Topical issue: Optical Nanostructuring
- Editorial
- Next-generation lithography – an outlook on EUV projection and nanoimprint
- Tutorial
- Photoresists in extreme ultraviolet lithography (EUVL)
- Review Articles
- Light sources for high-volume manufacturing EUV lithography: technology, performance, and power scaling
- Characterization and mitigation of 3D mask effects in extreme ultraviolet lithography
- EUV mask defectivity – a process of increasing control toward HVM
- Development and performance of EUV pellicles
- A review of nanoimprint lithography for high-volume semiconductor device manufacturing
- Large area nanoimprint by substrate conformal imprint lithography (SCIL)
- Laser interference patterning methods: Possibilities for high-throughput fabrication of periodic surface patterns
- Research Articles
- A full-process chain assessment for nanoimprint technology on 200-mm industrial platform
- Challenges of anamorphic high-NA lithography and mask making
- Research Article
- Chip bonding of low-melting eutectic alloys by transmitted laser radiation
Artikel in diesem Heft
- Cover and Frontmatter
- Views
- Patterning roadmap: 2017 prospects
- Community
- Conference Notes
- News from the European Optical Society (EOS)
- Topical issue: Optical Nanostructuring
- Editorial
- Next-generation lithography – an outlook on EUV projection and nanoimprint
- Tutorial
- Photoresists in extreme ultraviolet lithography (EUVL)
- Review Articles
- Light sources for high-volume manufacturing EUV lithography: technology, performance, and power scaling
- Characterization and mitigation of 3D mask effects in extreme ultraviolet lithography
- EUV mask defectivity – a process of increasing control toward HVM
- Development and performance of EUV pellicles
- A review of nanoimprint lithography for high-volume semiconductor device manufacturing
- Large area nanoimprint by substrate conformal imprint lithography (SCIL)
- Laser interference patterning methods: Possibilities for high-throughput fabrication of periodic surface patterns
- Research Articles
- A full-process chain assessment for nanoimprint technology on 200-mm industrial platform
- Challenges of anamorphic high-NA lithography and mask making
- Research Article
- Chip bonding of low-melting eutectic alloys by transmitted laser radiation
