Volume 3, Issue 2 -

The focus of this review is an introduction to chemiresistive chemical sensors. The general concept of chemical sensors is briefly introduced, followed by different architectures of chemiresistive sensors and relevant materials. For several of the most common systems, the fabrication of the active materials used in such sensors and their properties are discussed. Furthermore, the sensing mechanism, advantages, and limitations of each group of chemiresistive sensors are briefly elaborated. Compared to electrochemical sensors, chemiresistive sensors have the key advantage of a simpler geometry, eliminating the need for a reference electrode. The performance of bulk chemiresistors can be improved upon by using freestanding ultra-thin films (nanomaterials) or field effect geometries. Both of those concepts have also been combined in a gateless geometry, where charge transport though a percolation network of nanomaterials is modulated via adsorbate doping.

Organic solar cells have the ability to transform solar energy efficiently and have a promising energy balance. Producing these cells is economical and makes use of methods of printing using inks built on solvents that are well-matched with a variety of cheap materials like flexible plastic or paper. The primary materials used to manufacture organic solar cells include carbon-based semiconductors, which are good light absorbers and efficient charge generators. In this article, we review previous research of interest based on morphology of polymer blends used in bulk heterojunction (BHJ) solar cells and introduce their basic principles. We further review computational models used in the analysis of surface behavior of polymer blends in BHJ as well as the trends in the field of polymer surface science as applied to BHJ photovoltaics. We also give in brief, the opportunities and challenges in the area of polymer blends on BHJ organic solar cells.

An architecture of 5.2/5.8-GHz dual-band on-off keying (DBOOK) modulated transmitter is designed in a 0.18-μm CMOS technology. The proposed DBOOK transmitter is used in the biosignal transmission system with high power efficiency and small area. To reduce power consumption and enhance output swing, two pairs of center-tapped transformers are used as both LC tank and source grounding choke for the designed voltage controlled oscillator (VCO). Switching capacitances are used to achieve dual band operations, and a complemented power combiner is used to merge the differential output power of VCO to a single-ended output. Besides, the linearizer circuits are used in the proposed power amplifier with wideband output matching to improve the linearity both at 5.2/5.8-GHz bands. The designed DBOOK transmitter is implemented by dividing it into two chips. One chip implements the dual-band switching VCO and power combiner, and the other chip implements a linear power amplifier including dual-band operation. The first chip drives an output power of 2.2mW with consuming power of 5.13 mW from 1.1 V supply voltage. With the chip size including pad of 0.61 × 0.91 m 2 , the measured data rate and transmission efficiency attained are 100 Mb/s and 51 pJ/bit, respectively. The second chip, for power enhanced mode, exhibits P1 dB of −9 dBm, IIP3 of 1 dBm, the output power 1 dB compression point of 12.42 dBm, OIP3 of about 21 dBm, maximum output power of 17.02/16.18 dBm, and power added efficiency of 17.13/16.95% for 5.2/ 5.8 GHz. The chip size including pads is 0:693 × 1:084mm 2 .

How to effectively enhance the reliability robustness in high-voltage (HV) BCD [(bipolar) complementary metal-oxide semiconductor (CMOS) diffusion metaloxide semiconductor (DMOS)] processes is an important issue. Influences of layouttype dependences on anti-electrostatic discharge (ESD) robustness in a 0.25-μm 60-V process will be studied in this chapter, which includes, in part (1), the traditional striped-type n-channel lateral-diffused MOSFET (nLDMOS), waffle-type nLDMOS, and nLDMOS embedded with a “ p-n-p ”-arranged silicon-controlled rectifier (SCR) devices in the drain side; and in part (2) a p-channel LDMOS (pLDMOS) with an embedded “ p-n-p-n-p ”-arranged-type SCR in the drain side (diffusion regions of the drain side is P + - N + - P + - N + - P + ). Then, these LDMOS devices are used to evaluate the influence of layout architecture on trigger voltage (V t1 ), holding voltage (V h ), and secondary breakdown current (I t2 ). Eventually, the sketching of the layout pattern of a HV LDMOS is a very important issue in the anti-ESD consideration. Also, in part (1), the waffle-type nLDMOS DUT contributes poorly to I t2 robustness due to the non-uniform turned-on phenomenon and a narrow channel width per unit finger. Therefore, the I t2 robustness of a waffle-type nLDMOS device is decreased about 17% as compared to a traditional striped-type nLDMOS device (reference DUT-1). The ESD abilities of traditional stripedtype and waffle-type nLDMOS devices with an embedded SCR (“p-n-p”-manner arrangement in the drain side) are better than a traditional nLDMOS 224.4% in average. Noteworthy, the nLDMOS-SCR with the “p-n-p” -arranged-type in the drainend is a good structure for the anti-ESD reliability especially in HV usages. Furthermore, in part (2) this layout manner of P + discrete-island distributions in the drain-side have some impacts on the anti-ESD and anti-latch-up (LU) immunities. All of their I t2 values have reached above 6 A; however, the major repercussion is that the V h value will be decreased about 66.7 ~ 73.7%.