Volume 66, Issue 4-5 - Special Issue: Solving Boolean Problems and Beyond; Guest Editors: Rolf Drechsler, Görschwin Fey and Oliver Keszöcze

In the classical CMOS technology, EXOR gates are considered expensive and impractical. Recently, the growing relevance of cryptography-related applications and emerging technologies has revived the interest in EXOR gates. In this contexts, it is therefore important to consider network representations that assume EXOR gates explicitly, since the non-EXOR gates have, in general, a higher cost than EXOR ones. As a result, the widely adopted And-Inverter Graph (AIG) logic networks, have recently evolved into the new XOR-AND Graph (XAG) multi-level logic representation, and the logic synthesis on XAGs mainly aims at reducing the number of AND nodes. In general, we call EXOR-based synthesis the synthesis methods that minimize the non-EXOR gates in a Boolean circuit. Projected Sum Of Product, PSOP, decomposition is an EXOR based technique that can be applied to any Boolean function as a very fast pre-processing step for further minimizing the circuit area in standard logic synthesis. In this paper, we exploit PSOP decomposition in EXOR-based synthesis. The experimental results validate the proposed pre-processing method in EXOR-based synthesis, showing an interesting gain in area, within the same time limit.

Two-level logic minimization is a well-established process that efficiently minimizes functions described in the Sum-of-Products (SOP) form. Current two-level SOP minimizes, like Espresso and Boom, produce optimum or near-optimum results regarding the SOP size. However, in this article we show that an SOP minimization conducted in the standard, multi-output way, significantly worsens the result of the subsequent multi-level synthesis, especially for sparsely-specified functions, regardless of the optimization process and the tool used. In conclusion, we propose using a single-output two-level SOP minimization for sparsely specified functions. In this way, the obtained circuits are sometimes multiple times smaller, while no significant deterioration has been observed for any other functions.

This paper proposes two approaches to design of arithmetic units. The first approach considers the result of calculations as the system of the positive polarity Reed-Muller expansions. The second approach decomposes arithmetic operations into a set of up to 5-input Boolean functions. Standard multipliers, multipliers by modulo, and composite operations in small-bit ranges are considered. An expression for the calculation of the most significant bit of modular multiplication is represented.

Truncated adders are widely used in applications where using lower bit-width is enough to generate the desired outputs. Truncated adders give benefits in area, power, and delay as compared to their non-truncated counterparts. While prior works deal with the formal verification of n -bit adders, there is no prior work dealing with the formal verification of unverified m-bit truncated adders using verified n-bit adder designs, where m < ${< } $ n . In this work, we propose a methodology that enables the verification for any truncated adder designs, irrespective of the architecture, called Extend and Reduce (EnR). EnR uses a three-step methodology to formally verify the truncated adders, which are considered as Design Under Verification (DUV). Firstly, it extends the bit-width of the DUV (truncated adder) to match with the nearest higher 2 n -bit adder, called an Extended Truncated Adder (ETA). Secondly, it reduces off-the-shelf formally verified golden reference adder design by forcing 0’s at the input bits to match it to the extended DUV design and re-synthesizing it to generate a Reduced Golden Adder (RGA). Lastly, a combinational equivalence check is then performed between the ETA and the RGA for formal verification. If the truncated adder is correct, the ETA and RGA are equivalent and vice versa. We evaluate a number and variety of adder designs to show the efficacy of the EnR methodology. We performed the formal verification using Binary Decision Diagrams (BDDs) and And-Inverter Graphs (AIGs). Lastly, we show the scalability of EnR methodology using adders up to a bit-width of 512 bits. ACM CCS Hardware → Arithmetic and datapath circuits; Combinational circuits; Equivalence checking; Functional verification; Electronic design automation.

Approximate computing is an fast developing area for resource-efficient and fast designs that trades off computational accuracy with non-functional aspects such as delay, energy requirements or area. It can be used for applications where it is acceptable to compute inaccurate results such as image processing. A lot of work has been published on approximate synthesis for ASICs. As FPGAs are becoming more prevalent, approximation techniques for this technology should be developed. Lookup tables are a scarce resource on FPGAs. Consequently, we present and evaluate multiple approaches for reducing the number of lookup tables required to implement a given design on an FPGA. Our approaches work by removing either wires or entire lookup tables from a lookup table network. We can show that our approach is faster than related work while removing a comparable number of lookup tables (more in most cases).

A significant challenge hindering the widespread adoption of approximate hardware units is the complexity associated with test and error evaluation. We address this issue by extending Information Flow Tracking (IFT) for hardware designs to accommodate approximate units. Unlike conventional IFT approaches, our system employs a dynamic, error-responsive tag-based mechanism that facilitates tracking the error characteristics and their propagation within approximate units. Such an approach is vital in the domain of approximate computing, where uncommon yet substantial errors, such as those found in Equal Segmentation Adders (ESA), can markedly influence computation accuracy and reliability. By focusing on the dynamic nature of errors and their traceability, our methodology supports understanding the effects of approximation errors, thereby promoting their broader utilisation in various applications. The results of our study demonstrate the potential of analysing error propagation in approximate designs.

This paper deals with the very hard problem of grid coloring that has been specified more than 10 years ago in S. Fenner et al., Rectangle Free Coloring of Grids , 2009. Available at: http://www.cs.umd.edu/∼gasarch/papers/grid.pdf. It was unknown whether rectangle-free completely four-colored square grids of sizes 17 × 17 and 18 × 18 exist. As result of an extensive research I computed commonly with Christian Posthoff a rectangle-free pattern that can be reused cyclic-rotated by 90° for the four colors of the grid of size 18 × 18 (B. Steinbach and C. Posthoff, “Extremely complex 4-colored rectangle-free grids: solution of open multiple-valued problems,” in Proceedings of the IEEE 42nd International Symposium on Multiple-Valued Logic , Victoria, BC, Canada, ISMVL, 2012, pp. 37–44, B. Steinbach and C. Posthoff, “Rectangle-free colorings of extremely complex grids using 4 colors,” J. Mult.-Valued Log. Soft Comput. , vol. 21, nos. 5–6, pp. 609–625, 2013). A similar solution for the grid of size 17 × 17 has not been found so far. We explore in this paper for which sizes of square grids rectangle-free four-colored patterns exist, at which the pattern of one color can be reused for another color after a rotation by 90°.

Explaining and understanding AI-generated policies of control problems is crucial for the acceptance of such policies. Based on an optimisation challenge that took place at GECCO 2024, we describe different solutions for optimising generated policies for the well-known game 2048. At the same time, these generated policies aim to be simpler to understand and, thus, their decisions explainable in contrast to current solutions for 2048, as, e.g., neural network-based models. Our approach uses only Boolean expressions in the policy, and the optimisation shows that such a policy has advantages compared to more complex policy variants. The optimisation generates better results in a shorter time than for non-Boolean expressions. Additionally, the Boolean policies are smaller in size and can be reduced even more when applying existing techniques for term rewriting and simplification. These simplifications, again, may aid in understanding the policy’s decision.