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Structural bias in synthesis of sparsely-specified functions

  • Petr Fišer received his MSc. and Ph.D. degrees in Computer Science and Engineering at the Czech Technical University in Prague in 2002 and 2007, respectively. He currently works as an associate professor at the same university, Faculty of Information Technology. His main areas of interest are logic synthesis, two-level and multi-level optimization, build-in self-test (BIST), test generation, compression and on-line testing.

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    Jan Schmidt received his MSc. and Ph.D. degrees in Computer Science and Engineering at the Czech Technical University in Prague in 1976 and 2001, respectively. He currently works as an associate professor at the same university, Faculty of Information Technology. His main areas of interest are logic synthesis, two-level and multi-level optimization, machine-learning, and EDA.

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Published/Copyright: February 10, 2025
it - Information Technology
From the journal it - Information Technology Volume 66 Issue 4-5

Abstract

Two-level logic minimization is a well-established process that efficiently minimizes functions described in the Sum-of-Products (SOP) form. Current two-level SOP minimizes, like Espresso and Boom, produce optimum or near-optimum results regarding the SOP size. However, in this article we show that an SOP minimization conducted in the standard, multi-output way, significantly worsens the result of the subsequent multi-level synthesis, especially for sparsely-specified functions, regardless of the optimization process and the tool used. In conclusion, we propose using a single-output two-level SOP minimization for sparsely specified functions. In this way, the obtained circuits are sometimes multiple times smaller, while no significant deterioration has been observed for any other functions.

Keywords: incompletely specified functions; logic synthesis; structural bias; two-level minimization
Corresponding author: Petr Fišer, Faculty of Information Technology, Department of Digital Design, Czech Technical University in Prague, Prague, Czech Republic, E-mail: 

About the authors

Petr Fišer

Petr Fišer received his MSc. and Ph.D. degrees in Computer Science and Engineering at the Czech Technical University in Prague in 2002 and 2007, respectively. He currently works as an associate professor at the same university, Faculty of Information Technology. His main areas of interest are logic synthesis, two-level and multi-level optimization, build-in self-test (BIST), test generation, compression and on-line testing.

Jan Schmidt

Jan Schmidt received his MSc. and Ph.D. degrees in Computer Science and Engineering at the Czech Technical University in Prague in 1976 and 2001, respectively. He currently works as an associate professor at the same university, Faculty of Information Technology. His main areas of interest are logic synthesis, two-level and multi-level optimization, machine-learning, and EDA.

Acknowledgment

Computational resources were provided by the e-INFRA CZ project (ID: 90254), supported by the Ministry of Education, Youth and Sports of the Czech Republic.

  1. Research ethics: Not applicable.

  2. Informed consent: Not applicable.

  3. Author contributions: All authors have accepted responsibility for the entire content of this manuscript and approved its submission.

  4. Use of Large Language Models, AI and Machine Learning Tools: None declared.

  5. Conflict of interest: All other authors state no conflict of interest.

  6. Research funding: None declared.

  7. Data availability: Not applicable.

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Received: 2024-08-11
Accepted: 2024-12-16
Published Online: 2025-02-10
Published in Print: 2024-08-26

© 2025 Walter de Gruyter GmbH, Berlin/Boston

Articles in the same Issue

  1. Frontmatter
  2. Editorial
  3. Solving Boolean Problems and Beyond
  4. Research Articles
  5. PSOP decomposition for EXOR-based synthesis
  6. Structural bias in synthesis of sparsely-specified functions
  7. Two approaches of arithmetic units design
  8. EnR: extend and reduce methodology to enable formal verification of truncated adders
  9. Approximate synthesis for LUT count reduction via probabilistic error propagation
  10. Detailed insight into approximate circuits with error-responsive information flow tracking
  11. Rectangle-free four-colored square grids realized by cyclic-rotated reusable patterns
  12. Why less is sometimes more
https://doi.org/10.1515/itit-2024-0071
Keywords for this article
incompletely specified functions; logic synthesis; structural bias; two-level minimization

Articles in the same Issue

  1. Frontmatter
  2. Editorial
  3. Solving Boolean Problems and Beyond
  4. Research Articles
  5. PSOP decomposition for EXOR-based synthesis
  6. Structural bias in synthesis of sparsely-specified functions
  7. Two approaches of arithmetic units design
  8. EnR: extend and reduce methodology to enable formal verification of truncated adders
  9. Approximate synthesis for LUT count reduction via probabilistic error propagation
  10. Detailed insight into approximate circuits with error-responsive information flow tracking
  11. Rectangle-free four-colored square grids realized by cyclic-rotated reusable patterns
  12. Why less is sometimes more
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