Implementation of cascaded H-bridge DC-link inverter for marine electric propulsion drives

Introduction

In recent years, mechanically coupled ship propulsion systems are progressively being replaced by all electric propulsion drive systems. The replacement of mechanical couplings with an electrical systems, offers numerous benefits such as increased reliability, enhanced dynamic performance, reduced maintenance cost, more flexibility in ship layout design and reduced fuel consumption. The block diagram of electric propulsion drive system for marine applications is shown in Figure 1. It consists of turbine coupled with generator, phase shifting transformer, rectifier, and power inverter, motor drive applied to propeller and thruster loads. This paper mainly focused on power inverter to improve the power quality of electric propulsion drive for marine applications.

Figure 1:

Block diagram of electric propulsion drive system for marine applications.

The single line representation of power converter fed electric drive is shown in Figure 2 along with possible improvements and design choices for power converter and electric drive respectively. Power converter is a combination of rectifier integrated with an inverter.

Figure 2:

Power converter fed electric drive.

The possible improvements for power inverter to enhance the power quality can be done in two ways mainly: one by using MLIs with less power devices and other by utilizing advanced Pulse Width Modulation (PWM) methods (Naderi et al. 2021; Poorfakhraei, Narimani, and Emadi 2021a; Sunddararaj and Rangarajan 2020). The design choices for an electric drive to attain maximum torque for electric propulsion system can be done by using induction motor and permanent magnet motor drives (Caroline and Beno 2021). Multilevel Inverters (MLIs) are utilized as a favorable elucidation for power quality improvement, to produce high voltage and to attain maximum torque at the propeller shaft in marine electric propulsion drives (Lee and Lee 2021; Poorfakhraei, Narimani, and Emadi 2021a). The existing MLIs are also called as classical MLIs categorized into three types mainly, they are named as Capacitor-Clamped (CC), Diode-Clamped (DC) and Cascaded H-Bridge (CHB) MLIs (Bughneda et al. 2021). These MLIs are consists of more number of devices in terms of power devices or power diodes or capacitors by increasing the number of levels (Hegde, Rao, and Indira 2021; Salem et al. 2020). Therefore, classical MLIs increases cost, control complexity and needs more installation area (Vemuganti et al. 2021). To overcome these drawbacks, this paper proposed a CHBDCL inverter with less power devices compared with classical MLIs (Manjunatha et al. 2020). The Cascaded H-Bridge DC-Link (CHBDCL) inverter necessitates only ‘m + 3’ power devices for ‘m’ number of levels, although the classical MLIs requires ‘2(m − 1)’ power devices (Balal et al. 2022; Kubendran, Shuaib, and Roselyn 2022; Rao, Kumar, and Babu 2013). For example, the classical MLIs and CHBDCL inverter requires ten and twelve power devices respectively to generate seven level inverter output (Hassan et al. 2020; Rao, Kumar, and Veerabhadra 2022). Also, this percentage of reduction in power devices still can be increased by increasing number of levels. Using different PWM approaches, the CHBDCL inverter may achieve optimal performance (Easley, Shadmand, and Abu-Rub 2021; Rao, Veerabhadra, and Kumar 2020; Stöttner, Hanzl, and Endisch 2022). In this paper unipolar sine/space vector references with inverted sine carrier modulation techniques are considered for CHBDCL inverter to improve the power quality for marine electric propulsion drives. Finally, prototype model developed for single-phase seven level CHBDCL inverter using Field Programmable Gate Array (FPGA) and validated the simulation results for various modulation indices in terms of voltage levels and harmonic analysis.

CHBDCL inverter configuration

The structure of single-phase seven level CHBDCL inverter is depicted in Figure 3. It consists of a three separate DC sources, 10 power devices and an H-bridge inverter. Table 1 gives a number of parts comparison to generate single-phase seven level output phase voltage across load for the classical MLIs and CHBDCL inverter. The switching table of CHBDCL to generate the single-phase seven levels is given in Table 3. In this structure, DC sources are equal in magnitude i.e., V_dci = V_dc, where i = 1, 2 and 3.

The sum of all DC sources equals the maximum value of CHBDCL output voltage, and is given in (1).

with the help of H-bridge inverter, the positive levels (i.e., 0, +V_dc, +2V_dc and 3V_dc) and negative levels (i.e., −V_dc, −2V_dc and −3V_dc) are obtained. The seven level stepped output voltage at the load can be obtained using (2) and (3)

Figure 3:

Seven level CHBDCL inverter (single-phase).

The number of output voltage levels i.e., M_Levels of CHBDCL inverter can be obtained by the Equation (4):

where ‘P’ is the number of DC sources and ‘Q’ is the number of H-bridges.

The number of power devices for the CHBDCL inverter can be assessed by using Equation (5).

From Table 2, it is self-evident that as the number of levels in the proposed CHBDCL inverter grows, the number of individual components will naturally decrease.

Figure 4 indicates the variation of power switches for existing MLI’s and CHBDCL inverter with respect to number of levels. It can be noticed that the power switches in the proposed CHBDCL inverter drastically reduced when compared to existing MLI’s.

Figure 4:

Variation of power switches with respect to number of levels.

PWM scheme

The Sine and Space vector PWM techniques are considered for proposed work. The carrier wave chosen to be a level shifted sinusoid operating at 5 kHz frequency. Figure 5 represents the unipolar sine PWM technique.where in a 5 kHz level shifted sinusoid carrier compared with a unipolar sinusoid at 50 Hz. Figure 6 shows the space vector PWM technique, the carrier wave is a sinusoid with 5 kHz like sine PWM but the reference wave is unipolar space vector reference.

Figure 5:

Unipolar SPWM with sine wave carrier.

The range of Modulation index ‘M’ for sine reference is varies from 0 to 1 and for space vector reference is varies from 0 to 0.866 (Figure 6).

where ‘m’ denotes the number of levels, ‘A_r’ denotes amplitude of reference and ‘A_c’ denotes amplitude of carrier.

Figure 6:

Unipolar SVPWM with sine carrier.v

From Equation (6), the expression for ‘M’ to generate seven level waveform is given by Equation (7).

Results and discussion of proposed CHBDCL inverter

This section elaborates the simulation and practical outcomes of the proposed CHBDCL inverter for seven level. The Figures 7–15 gives the complete information of the theoretical and practical results obtained for SPWM and SVPWM techniques. The output voltage and the %THD for various modulation indices are compared. The entire results are summarized in the Tables 4 and 5. After careful observation it’s evident that the simulation and practical outcomes obtained are in good agreement.

Figure 7:

Output voltage for SPWM technique.

Figure 8:

Output voltage for SVPWM technique.

Figure 9:

%THD levels for SPWM technique.

Figure 10:

%THD levels for SVPWM technique.

Figure 11:

Experimental setup for proposed 7 level CHBDCL inverter.

Figure 12:

Pulses generated from experimental setup for unipolar SPWM.

Figure 13:

Pulses generated from experimental setup for SVPWM.

Figure 14:

SPWM experimental output voltage with %THD.

Figure 15:

SVPWM experimental output voltage with %THD.

The Tables 4 and 5 gives the comparisons of THD and output voltage levels for different modulation techniques. For a modulation index of 0.9 the SPWM techniques gives simulation and practical THD of 24.57 and 23.48% respectively. Similarly for the same modulation index of 0.9 the SVPWM technique gives simulation and practical THD 19.13 and 18.07% respectively. The output voltages for SPWM and at 0.9 modulation index are 190.1 and 189.2 V respectively in simulation and practical analysis. The output voltages for SVPWM and at 0.9 modulation index are 216.2 and 215.1 V respectively in simulation and practical analysis. So it can be concluded that the SVPWM technique gives better output voltage and low THD levels when compared with SPWM.

Conclusion

In this paper CHBDCL inverter configuration for seven level has been accessed in terms of harmonic analysis by using SPWM and SVPWM approaches. It is concluded that the proposed CHBDCL inverter necessitates only ‘10’ power devices for seven levels, whereas the classical MLIs requires ‘12’ power devices. Furthermore, with increasing levels the required power devices decreases which decreases the hardware complexity. In addition, the proposed CHBDCL inverter requires less installation area and cost-effective. Further, simulation and hardware results of CHBDCL inverter using SPWM and SVPWM approaches are included to verify the harmonic analysis. It is concluded that, CHBDCL inverter using SVPWM has given less %THD compared to SPWM. Finally, the simulation results of CHBDCL inverter has been validated with prototype model using FPGA based pulse generation.