Startseite Mathematik An energy-efficient FPGA-based implementation of AES algorithm using HSTL IO standards for new digital age technologies
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An energy-efficient FPGA-based implementation of AES algorithm using HSTL IO standards for new digital age technologies

  • Chandrashekhar Patel , Bhanu Priya Yadav und Aditi Saxena
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Algorithms
Ein Kapitel aus dem Buch Algorithms

Abstract

Our daily activities in the new digital age are heavily reliant on the internet. Online communication is used for many purposes, including leisure, commerce, and work-related activities. It suggests that a significant amount of data being exchanged online. Therefore, the researcher is concentrating on security to stop threats and online vulnerabilities. To make digital communication quick and secure, the authors used an energy-efficient FPGA-based implementation of the AES algorithm. The XPA (XPower Analyzer) tool is used to analyze total power usage throughout the experimental activity, and the Vivado IDE tool is utilized for simulation using the Verilog language. To calculate the overall amount of power consumed with voltages ranging from 0.95 to 1.20 V, voltage scaling is applied. The average total power consumption of the IO standard family HSTL_I, according to the researcher’s analysis, is 0.0938 W that is less than that of the other IO standard families, making it the most appropriate for our digital component.

Abstract

Our daily activities in the new digital age are heavily reliant on the internet. Online communication is used for many purposes, including leisure, commerce, and work-related activities. It suggests that a significant amount of data being exchanged online. Therefore, the researcher is concentrating on security to stop threats and online vulnerabilities. To make digital communication quick and secure, the authors used an energy-efficient FPGA-based implementation of the AES algorithm. The XPA (XPower Analyzer) tool is used to analyze total power usage throughout the experimental activity, and the Vivado IDE tool is utilized for simulation using the Verilog language. To calculate the overall amount of power consumed with voltages ranging from 0.95 to 1.20 V, voltage scaling is applied. The average total power consumption of the IO standard family HSTL_I, according to the researcher’s analysis, is 0.0938 W that is less than that of the other IO standard families, making it the most appropriate for our digital component.

Heruntergeladen am 19.10.2025 von https://www.degruyterbrill.com/document/doi/10.1515/9783111229157-003/html
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