Volume 64, Issue 3 - Approximate Computing / Guest Editor: Oliver Keszocze, Host Editor: Görschwin Fey

Approximate computing has become an emerging research topic for energy-efficient design of circuits and systems. Many approximate arithmetic circuits have been proposed, therefore it is critical to summarize the available approximation techniques to improve performance and energy efficiency at a acceptable accuracy loss. This paper presents an overview of circuit-level techniques used for approximate arithmetic. This paper provides a detailed review of circuit-level approximation techniques for the arithmetic data path. Its focus is on identifying critical circuit-level approximation techniques that apply to computational units and blocks. Approximate adders, multipliers, dividers, and squarer are introduced and classified according to their approximation methods. FFT and MAC are discussed as computational blocks that employ an approximate algorithm for implementation.

We present the design and a closed-form error analysis of accuracy-configurable multipliers via segmented carry chains. To address this problem, we model the approximate partial-product accumulations as a sequential process. According to a given splitting point of the carry chains, the technique herein discussed allows varying the quality of the accumulations and, consequently, the overall product. Due to these shorter critical paths, such kinds of approximate multipliers can trade-off accuracy for an increased performance whilst exploiting the inherent area savings of sequential over combinatorial approaches. We implemented multiple architectures targeting FPGAs and ASICs with different bit-widths and accuracy configurations to 1) estimate resources, power consumption, and delay, as well as to 2) evaluate those error metrics that belong to the so-called #P-complete class.

With ReRAM being a non-volative memory technology, which features low power consumption, high scalability and allows for in-memory computing, it is a promising candidate for future computer architectures. Approximate computing is a design paradigm, which aims at reducing the complexity of hardware by trading off accuracy for area and/or delay. In this article, we introduce approximate computing techniques to in-memory computing. We extend existing compilation techniques for the Programmable Logic in-Memory (PLiM) computer architecture, by adapting state-of-the-art approximate computing techniques for arithmetic circuits. We use Cartesian Genetic Programming for the generation of approximate circuits and evaluate them using a Symbolic Computer Algebra-based technique with respect to error-metrics. In our experiments, we show that we can outperform state-of-the-art handcrafted approximate adder designs.

Approximate Computing (AC) and Stochastic Computing (SC) have been studied as new computing paradigms to achieve energy-efficient designs for error-tolerant applications. The hardware cost of SC generally can be small compared to that of AC, but SC has not been applied to a wide range of applications as AC because SC needs very long cycles to use long random bit strings called Stochastic Numbers (SNs) when we need to maintain the desired precision. To mitigate this disadvantage of SC, we propose a new idea to approximate numbers represented by SNs; our idea is to use multiple SNs to represent one number. Indeed our method can shorten the length of SNs drastically while keeping the precision level compared to conventional SNs. We study two specific cases where we use two and three shorter bit-strings to represent a single conventional SN, which we call a dual-rail and a triple-rail SNs, respectively. We also discuss a general case when we use many SNs corresponding to a single conventional SNs. We also compare triple-rail, dual-rail and conventional SNs in terms of hardware overhead and calculation errors in this paper. From the comparison, we can conclude that our idea can be used to shorten the necessary cycles for SC.