Abstract
When the traditional planar metal-oxide-semiconductor-field-effect transistors (MOSFETs) encounter insurmountable bottleneck of static power dissipation, junctionless transistor (JLT) becomes a promising candidate for sub-22 nm nanoscale devices due to its simpler fabrication process and better short-channel performances. Subthreshold behaviors dominate the standby power of nanoscale JLTs. In this chapter, a physics-based analytical model of electrostatic potential for both silicon and germanium short-channel junctionless cylindrical surrounding-gate (JLCSG) MOSFETs operated in the subthreshold regime is proposed, in which the full twodimensional (2D) Poisson’s equation is solved in the channel region by a method of series expansion. The expression of the proposed electrostatic potential is completely rigorous and explicit. Based on this result, the expressions of threshold voltage, subthreshold drain current, and subthreshold swing for JLCSG MOSFETs are derived. Subthreshold behaviors are studied in detail by changing different device parameters and bias conditions, including doping concentration, channel radius, gate length, gate equivalent oxide layer thickness, drain voltage, and gate voltage. Results predicted by all the analytical models agree well with numerical solutions from the three-dimensional simulator. These analytical models can be used to investigate the operating mechanisms of nanoscale JLCSG MOSFETs and to optimize their device performances.
Acknowledgment
This work was funded in part by the National Science and Technology Major Project (No. 2011ZX02708-002 and No. 2013ZX02303-003), the Tsinghua National Laboratory for Information Science and Technology (TNList) Cross-discipline Foundation, and by the National Natural Science Foundation of China (No. 61306105).
References
[1] Kahng D, Atalla M M. Silicon–silicon dioxide field induced surface devices. InThe IRE Solid-State Device Res. Conf . Pittsburgh, PA, 1960.Suche in Google Scholar
[2] Schaller R R. Moore’s law: Past, present and future. Spectrum, IEEE 1997, 34, 52–9.10.1109/6.591665Suche in Google Scholar
[3] Gusev E P, Buchanan D A, Cartier E, Kumar A, DiMaria D, Guha S, AjmeraA. Ultrathin high-K gate stacks for advanced CMOS devices. InElectron Devices Meeting, 2001. IEDM’01. Technical Digest, IEEE 2001, 20–1.Suche in Google Scholar
[4] Collaert N, Keersgieter A D, Dixit A, Ferain I, Lai L S, Lenoble D, Jurczak M. Multi-gate devices for the 32nm technology node and beyond. Solid State Electron . 2008, 52, 1291–6.10.1109/ESSDERC.2007.4430899Suche in Google Scholar
[5] Colinge J P, Lee C W, Afzalian A, Akhavan N D, Yan R, Ferain I, Murphy R. Nanowire transistors without junctions. Nature Nanotechnol . 2010, 5, 225–9.10.1038/nnano.2010.15Suche in Google Scholar PubMed
[6] Lee C W, Ferain I, Afzalian A, Yan R, Akhavan N D, Razavi P, Colinge J P. Performances estimation of junctionless multigate transistors. Solid State Electron . 2010, 54, 97–103.10.1016/j.sse.2009.12.003Suche in Google Scholar
[7] Colinge J P, Lee C W, Ferain I, Akhavan N D, Yan R, Razavi P, Doria R T. Reduced electric field in junctionless transistors. Appl. Phys. Lett . 2010, 96, 073510.10.1063/1.3299014Suche in Google Scholar
[8] Su C J, Tsai T I, Liou Y L, Lin Z M, Lin H C, Chao T S. Gate-all-around junctionless transistors with heavily doped polysilicon nanowire channels. IEEE Electron Devices Lett . 2011, 32, 521–3.10.1109/LED.2011.2107498Suche in Google Scholar
[9] Barraud S, Berthomé M, Coquand R, Cassé M, Ernst T, Samsonm M P, Poiroux T. Scaling of trigate junctionless nanowire MOSFET with gate length down to 13 nm. IEEE Electron Devices Lett . 2012, 33, 1225–7.10.1109/LED.2012.2203091Suche in Google Scholar
[10] Lee C-W, Nazarov A N, Ferain I, Akhavan N D, Yan R, Razavi P, et al. Low subthreshold slope in junctionless multigate transistors. Appl. Phys. Lett . 2010, 96, 102–106.10.1063/1.3358131Suche in Google Scholar
[11] Song Y, Zhang C, Dowdy R, Chabak K, Mohseni P K, Choi W, et al. III–V Junctionless gate-all-around nanowire MOSFETs for high linearity low power applications. IEEE Trans. Electron Dev. 2014, 35, 324–6.10.1109/LED.2013.2296556Suche in Google Scholar
[12] Gundapaneni S, Ganguly S, Kottantharayil A. Bulk planar junctionless transistor (BPJLT): An attractive device alternative for scaling. IEEE Electron Devices Lett . 2011, 32, 261–3.10.1109/LED.2010.2099204Suche in Google Scholar
[13] Colinge J P. FinFETs and Other Multi-Gate Transistors, Springer, New York, 2008.10.1007/978-0-387-71752-4Suche in Google Scholar
[14] Pillarisetty R. Academic and industry research progress in germanium nano devices. Nature 2011, 479, 324–8.10.1038/nature10678Suche in Google Scholar PubMed
[15] Brunco D P, Jaeger B D, Eneman G, Mitard J, Hellings G, Satta A, Heyns M M. Germanium MOSFET devices: Advances in materials understanding, process development, and electrical performances. J. Electrochem. Soc. 2008, 155, 552–61.10.1149/1.2919115Suche in Google Scholar
[16] Rosenberg J J, Martin S C. Self-aligned germanium MOSFETs using a nitrided native oxide gate insulator. IEEE Electron Devices Lett . 1988, 9, 639–40.10.1109/55.20421Suche in Google Scholar
[17] Thareja G, Liang J, Chopra S, Adams B, Patil N, Cheng S L, Nishi Y. High performances germanium n-MOSFET with antimony dopant activation beyond 1×1020 cm–3. IEDM Tech. Dig 2010, 245–8.10.1109/IEDM.2010.5703336Suche in Google Scholar
[18] Whang S J, Lee S J, Gao F, Wu N, Zhu C X, Pan J S, Kwong D L. Germanium p-& n-MOSFETs fabricated with novel surface passivation (plasma-PH 3 and thin AlN) and TaN/HfO 2 gate stack. IEDM Technical Digest. 2004, 307–10.10.1109/IEDM.2004.1419140Suche in Google Scholar
[19] Chui C O, Kim H, McIntyre P C, Saraswat K C. A germanium NMOSFET process integrating metal gate and improved hi-/spl kappa/dielectrics. In Electron Devices Meeting, 2003. IEDM’03 Technical Digest 2003, 18.3.1–18.3.4.Suche in Google Scholar
[20] Shang H, Lee K L, Kozlowski P, D’Emic C, Babich I, Sikorski E, Haensch W. Self-aligned n-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric and tungsten gate. IEEE Electron Devices Lett. 2004, 25, 135–7.10.1109/LED.2003.823060Suche in Google Scholar
[21] Kabuyanagi S, Nishimura T, Nagashio K, Toriumi A. High electron mobility in Germanium junctionless n-MOSFETs. ECS Trans . 2013, 58, 309–15.10.1149/05809.0309ecstSuche in Google Scholar
[22] Synopsys. T. Sentaurus User’s Manual, Version D-2010.03, 2010.Suche in Google Scholar
[23] Lee C W, Borne A, Ferain I, Afzalian A, Yan R, Akhavan N D, Colinge J P. High-temperature performances of silicon junctionless MOSFETs. IEEE Trans. Electron Dev. 2010, 57, 620–5.10.1109/TED.2009.2039093Suche in Google Scholar
[24] Choi S J, Moon D I, Kim S, Duarte J P, Choi Y K. Sensitivity of threshold voltage to nanowire width variation in junctionless transistors. IEEE Electron Devices Lett . 2011, 32, 125–7.10.1109/LED.2010.2093506Suche in Google Scholar
[25] Souza M D, Pavanello M A, Trevisoli R D, Doria R T, Colinge J. Cryogenic operation of junctionless nanowire transistors. IEEE Electron Devices Lett . 2011, 32, 1322–4.10.1109/LED.2011.2161748Suche in Google Scholar
[26] Juan P D, Choi S J, Choi Y K. A full-range drain current model for double-gate junctionless transistors. IEEE Trans. Electron Dev . 2011, 58, 4219–25.10.1109/TED.2011.2169266Suche in Google Scholar
[27] Duarte J P, Choi S J, Moon D I, Choi Y K. A nonpiecewise model for long-channel junctionless cylindrical nanowire FETs. IEEE Electron Devices Lett . 2012, 33, 155–7.10.1109/LED.2011.2174770Suche in Google Scholar
[28] Jin X S, Liu X, Hyuck-In K, Jong-Ho L. A continuous current model of accumulation mode (junctionless) cylindrical surrounding-gate nanowire MOSFETs. Chin. Phys. Lett . 2013, 30, 038502-1–038502-4.10.1088/0256-307X/30/3/038502Suche in Google Scholar
[29] Kim S K, Kim W D, Kim K M, Hwang C S, Jeong J. High dielectric constant TiO2 thin films on a Ru electrode grown at 250 C by atomic-layer deposition. Appl. Phys. Lett . 2004, 85, 4112–4.10.1063/1.1812832Suche in Google Scholar
[30] Georgiev Y M, Yu R, Petkov N, Lotty O, Nightingale A M, Duffy R, Holmes J D. Silicon and germanium junctionless nanowire transistors for sensing and digital electronics applications. InFunctional Nanomaterials and Devices for Electronics, Sensors and Energy Harvesting 2014, 367–88.10.1007/978-3-319-08804-4_17Suche in Google Scholar
[31] Kao J, Chandrakasan A, Antoniadis D. Transistor sizing issues and tool for multi-threshold CMOS technology. InProceedings of the 34th Annual Design Automation Conference 1997, 409–14.10.1109/DAC.1997.597182Suche in Google Scholar
[32] Sorée B, Magnus W, Pourtois G. Analytical and self-consistent quantum mechanical model for a surrounding gate MOS nanowire operated in JFET mode. J. Comput. Electron. 2008, 7, 380–3.10.1007/s10825-008-0217-3Suche in Google Scholar
[33] Cheralathan M, Cerdeira A, Iniguez B. Compact model for long-channel cylindrical surrounding-gate MOSFETs valid from low to high doping concentrations. Solid State Electron. 2011, 55, 13–8.10.1016/j.sse.2010.08.015Suche in Google Scholar
[34] T.-K. Chiang. A new quasi-2-D threshold voltage model for short-channel junctionless cylindrical surrounding gate (JLCSG) MOSFETs. IEEE Trans. Electron Dev . 2012, 59, 3127–9.10.1109/TED.2012.2212904Suche in Google Scholar
[35] Hu G, Xiang P, Ding Z, Liu R, Wang L, Tang T. Analytical models for electric potential, threshold voltage, and subthreshold swing of junctionless surrounding-gate transistors. IEEE Trans. Electron Dev. 2014, 61, 688–95.10.1109/TED.2013.2297378Suche in Google Scholar
[36] Chiang T K. A quasi-two-dimensional threshold voltage model for short-channel junctionless double-gate MOSFETs. IEEE Trans. Electron Dev . 2012, 59, 3127–9.10.1109/TED.2012.2202119Suche in Google Scholar
[37] Li C, Zhuang Y, Di S, Han R. Subthreshold behavior models for nanoscale short-channel junctionless cylindrical surrounding-gate MOSFETs. IEEE Trans. Electron Dev . 2013, 60, 3655–62.10.1109/TED.2013.2281395Suche in Google Scholar
[38] Jiang C, Liang R, Wang J, Xu J. A two-dimensional analytical model for short-channel junctionless double-gate MOSFETs. AIP Advances 2015, 5, 057122.10.1063/1.4921086Suche in Google Scholar
[39] Hu G X, Liu R, Tang T A, Ding S J, Wang L L. Theory of short-channel surrounding-gate metal–oxide–semiconductor field-effect-transistors. Jpn. J. Appl. Phys . 2007, 46, 1437.10.1143/JJAP.46.1437Suche in Google Scholar
[40] Masetti G, Severi M, Solmi S. Modeling of carrier mobility against carrier concentration in arsenic-, phosphorus-, and boron-doped silicon. IEEE Trans. Electron Dev. 1983, 30, 764–9.10.1109/T-ED.1983.21207Suche in Google Scholar
[41] Liu Z H, Hu C, Huang J H, Chan T Y, Jeng M C, Ko P K, Cheng Y C. Threshold voltage model for deep-submicrometer MOSFETs. IEEE Trans. Electron Dev. 1993, 40, 86–95.10.1109/16.249429Suche in Google Scholar
[42] Mutlu A A, Rahman M. Two-dimensional analytical model for drain induced barrier lowering (DIBL) in short-channel MOSFETs. InSoutheastcon, Proceedings of the IEEE 2002, 340–4.10.1109/SECON.2000.845589Suche in Google Scholar
[43] Kloes A, Weidemann M, Goebel D, Bosworth B T. Three-dimensional closed-form model for potential barrier in undoped FinFETs resulting in analytical equations for and subthreshold slope. IEEE Trans. Electron Dev . 2008, 55, 3467–75.10.1109/TED.2008.2006535Suche in Google Scholar
[44] Chen Q, Agrawal B, James D M. A comprehensive analytical subthreshold swing (S) model for double-gate MOSFETs. IEEE Trans. Electron Dev . 2002, 49, 1086–90.10.1109/TED.2002.1003757Suche in Google Scholar
[45] Mondal P, Ghosh B, Bal P. Planar junctionless transistor with non-uniform channel doping. Appl. Phys. Lett. 2013, 102, 133505.10.1063/1.4801443Suche in Google Scholar
[46] Choi W Y, Song J Y, Lee J D, Park Y J, Park B-G. A novel biasing scheme for I-MOS (impact-ionization MOS) devices. IEEE Trans. Nanotechnol. 2005, 4, 322–5.10.1109/TNANO.2005.847001Suche in Google Scholar
[47] Ionescu A M, Riel H. Tunnel field-effect transistors as energy efficient electronic switches. Nature 2011, 479, 329–37.10.1038/nature10679Suche in Google Scholar PubMed
[48] Akarvardar K, Eggimann C, Tsamados D, Singh C Y, Wan G C, Ionescu A M, Howe R T, Wong H S P. Analytical modeling of the suspended-gate FET and design insights for low-power logic. IEEE Trans. Electron Dev. 2008, 55, 48–59.10.1109/TED.2007.911070Suche in Google Scholar
[49] Salahuddin S, Datta S. Use of negative capacitance to provide voltage amplification for low power nanoscale devices. Nano Lett . 2008, 8, 405–10.10.1021/nl071804gSuche in Google Scholar PubMed
[50] Mitard J, Shea C, Jaeger D B, Pristera A, Wang G, Houssa M, et al. Impact of EOT scaling down to 0.85 nm on 70 nm Ge-pFETs technology with STI. InVLSI Symp. Tech. Dig . 2009, 82–3.Suche in Google Scholar
[51] Hellings G, Eneman G, Krom R, Jaeger D B, Mitard J, Keersgieter D A, Meyer D K. Electrical TCAD simulations of a germanium pMOSFET technology. IEEE Trans. Electron Dev . 2010, 57, 2539–46.10.1109/TED.2010.2060726Suche in Google Scholar
© 2018 Walter de Gruyter GmbH, Berlin/Boston
Artikel in diesem Heft
- CO2-based hydrogen storage: CO2 hydrogenation to formic acid, formaldehyde and methanol
- Computer analysis of potentiometric data of complexes formation in the solution
- Reactive extraction at liquid–liquid systems
- Grignard Reagents and Iron
- On-chip Wide Range Bidirectional Current Sensor for Li-ion Battery Management System
- Introduction to environmental engineering
- Subthreshold Behaviors of Nanoscale Silicon and Germanium Junctionless Cylindrical Surrounding-Gate MOSFETs
Artikel in diesem Heft
- CO2-based hydrogen storage: CO2 hydrogenation to formic acid, formaldehyde and methanol
- Computer analysis of potentiometric data of complexes formation in the solution
- Reactive extraction at liquid–liquid systems
- Grignard Reagents and Iron
- On-chip Wide Range Bidirectional Current Sensor for Li-ion Battery Management System
- Introduction to environmental engineering
- Subthreshold Behaviors of Nanoscale Silicon and Germanium Junctionless Cylindrical Surrounding-Gate MOSFETs