Startseite An enhanced implementation of SRF and DDSRF-PLL for three-phase converters in weak grid
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An enhanced implementation of SRF and DDSRF-PLL for three-phase converters in weak grid

  • Arkan A. Hussein ORCID logo EMAIL logo , Abdulbasit H. Ahmed und Natheer M. Mohammed
Veröffentlicht/Copyright: 21. März 2022

Abstract

Renewable energy generation systems connected to utility grid require perfect synchronization to grid which is one of the most important issues that needs to be taken into consideration. This paper proposed a hardware-accelerated implementation for the decoupled double synchronous reference frame phase-locked loop (DDSFR-PLL) for grid synchronization in grid-connected converters in weak grid that suffers from phase voltage-unbalance, variable phase and frequency conditions. Since the transformations and filtering of this method is computationally intensive and needs to be executed as fast as possible by the microcontroller unit (MCU) and Due to the presence of other current and voltage regulation loops in the same interrupt service routine (ISR) with high frequency rate, a hardware-based acceleration using the STM32G4x4 MCU built-in filter, filter math accelerator (FMAC) and coordinate rotation digital computer (CORDIC) is used to speed the execution time. This study addresses the description, derivation and implementation of the both DQ-PLL and DDSRF-PLL algorithms. The performance of both pure-software and accelerated implementation is demonstrated, compared and run on a three-level active neutral point clamped (ANPC) converter board. In proposed method, CPU load dropped from 80.5% by using the conventional software implementation to 23.6% (70% load reduction).This reduction in CPU load enables the addition of more features and more advanced current and voltage control algorithms.


Corresponding author: Arkan A. Hussein, Electrical Engineering Department, Tikrit University, Tikrit, Iraq, E-mail:

  1. Author contributions: All the authors have accepted responsibility for the entire content of this submitted manuscript and approved submission.

  2. Research funding: None declared.

  3. Conflict of interest statement: The authors declare no conflicts of interest regarding this article.

Appendix I: Inverter circuit parameters

Table 4:

Designed ANPC inverter key specifications.

Parameter Specifications
Output power 15 kW
Output voltage 3 PH + N 400 VAC
Output frequency 50 Hz
Output current 24 AAC (max.)
Nominal input voltage 800 VDC
Input voltage range 600–1100 VDC
Nominal input current 25 ADC
Switching frequency 50 kHz
Efficiency 99.2%
Weight 3.2 kg
Power density 1.5 kW/L

Appendix II: LCL filter design

The main component of output filter is L INV which is calculated by using Eq. (1):

(1) L INV = V DC 8 × f sw × I _ grid _ max × ripple _ percentage

where ripple percentage is the inductor ripple current to be selected to be 40% of the RMS current of the inverter, thus:

L INV = 1100 8 × 50 , 000 × 24 × 0.40 = 286 μH

Two NPF250040 cores were used for each inductor with 37 turns. This yielded a full load inductance of 299 μH.

The primary filter capacitor can be calculated by Eq. (2):

(2) C f = % Q rated 2 π f grid V grid 2

where %Q rated is the total reactive power absorbed by the capacitor which is limited by 5% of the total which is 15 kW/3 or 5 kW for each phase then:

C f = 0.05 × 5000 2 π × 50 × ( 400 3 ) 2 = 14.92 μ F 15 μ F

To find grid-side inductor value, the attenuation factor between grid inductor and inverter inductor is assumed to be 10%, then, the ratio between grid inductor and inverter inductor r computed from Eq. (3):

(3) r = 1 10 % 1 | 1 L GRID × C b × ( 2 × π × f sw ) 2 × % Q |

Or, r = 10 1 | 1 286 × 10 6 × 300 × 10 6 × ( 2 π 50,000 ) 2 × 0.05 | = 2.13 % .

So, the grid-side inductor value is:

L GRID = L INV × r = 2.13 % × 286 μ H = 6.1 μ H

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Received: 2021-10-08
Accepted: 2022-03-06
Published Online: 2022-03-21

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