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Ground plane and selective buried oxide based planar junctionless transistor

  • Asim M. Murshid ORCID logo and Faisal Bashir ORCID logo EMAIL logo
Published/Copyright: October 20, 2021
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Abstract

In this work, we demonstrate a ground plane (GP) based Selective Buried Oxide (SELBOX) Junctionless Transistor (JLT), named as GP-SELBOX-JLT. The use of GP and SELBOX in the proposed device reduces the electric field and enhances volume depletion in the channel, hence improves I ON/I OFF ratio and scalability. Using calibrated 2-D simulation, we have shown that proposed device exhibits better Short Channel Effect (SHE) immunity as compared to SOI-JLT. Therefore, the proposed GP-SELBOX-JLT can be scaled without degrading the performance in sub 20 nm regime. In addition, the ac study has shown that the cutoff frequency (f T) of GP-SELBOX-JLT is almost equal to conventional SOI-JLT.


Corresponding author: Faisal Bashir, PhD, Department of Electronics and Insutrumentation technology, University of Kashmir, Srinagar, J&K, India, E-mail:

  1. Author contributions: All the authors have accepted responsibility for the entire content of this submitted manuscript and approved submission.

  2. Research funding: None declared.

  3. Conflict of interest statement: The authors declare no conflicts of interest regarding this article.

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Received: 2021-03-09
Accepted: 2021-10-08
Published Online: 2021-10-20
Published in Print: 2022-01-27

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