Startseite Medizin Offset compensated baseline restoration and computationally efficient hybrid interpolation for the brain PET
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Offset compensated baseline restoration and computationally efficient hybrid interpolation for the brain PET

  • Saeed Mian Qaisar EMAIL logo
Veröffentlicht/Copyright: 6. Dezember 2018
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Abstract

The acquisition of positron emission tomography (PET) pulses introduces artifacts and limits the performance of the scanner. To minimize these inadequacies, this work focuses on the design of an offset compensated digital baseline restorer (BLR) along with a two-stage hybrid interpolator. They respectively treat the incoming pulse offsets and limited temporal resolution and improve the scanner performance in terms of calculating depth of interactions and line of responses. The offset of incoming PET pulses is compensated by the BLR and then their interesting parts are selected. The selected signal portion is up-sampled with a hybrid interpolator. It is composed of an optimized weighted least-squares interpolator (WLSI) and a simplified linear interpolator. The processes of calibrating the WLSI coefficients and characterizing the BLR and the interpolator modules are described. The functionality of the proposed modules is verified with an experimental setup. Results have shown that the devised BLR effectively compensates a dynamic range of bipolar offsets. The signal selection process allows focusing only on the relevant signal part and avoids the unnecessary operations during the post-interpolation process. Additionally, the hybrid nature allows improving the signal temporal resolution with an appropriate precession at a reduced computational complexity compared to the mono-interpolation-based arithmetically complex counterparts. The component-level architectures of the BLR and the interpolator modules are also described. It promises an efficient integration of these modules in modern PET scanners while using standard and economical analog-to-digital converters and field-programmable gate arrays. It avoids the development of high-performance and expensive application-specific integrated circuits and results in a cost-effective realization.

Acknowledgments

The author is thankful to the anonymous reviewers for their valuable feedback and to Drs. D. Liksonov, A. Bakkali, and N. Tamda for the fruitful discussions.

  1. Author contributions: All the authors have accepted responsibility for the entire content of this submitted manuscript and approved submission.

  2. Research funding: This project was funded by OSEO, UFC, France.

  3. Employment or leadership: None declared.

  4. Honorarium: None declared.

  5. Competing interests: The funding organization(s) played no role in the study design; in the collection, analysis, and interpretation of data; in the writing of the report; or in the decision to submit the report for publication.

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Received: 2018-09-15
Accepted: 2018-11-15
Published Online: 2018-12-06

©2018 Walter de Gruyter GmbH, Berlin/Boston

Heruntergeladen am 26.12.2025 von https://www.degruyterbrill.com/document/doi/10.1515/bams-2018-0031/pdf
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