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A 12-bit 1-MS/s 26-μW SAR ADC for Sensor Applications

  • Yung-Hui Chung EMAIL logo , Chia-Wei Yen and Cheng-Hsun Tsai
Published/Copyright: April 30, 2016
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Abstract

This chapter presents an energy-efficient 12-bit 1-MS/s successive approximation register analog-to-digital converter (ADC) for sensor applications. A programmable dynamic comparator is proposed to suppress static current and maintain good linearity. A hybrid charge redistribution digital-to-analog converter is proposed to decrease the total capacitance, which would reduce the power consumption of the input and reference buffers. In the proposed ADC, its total input capacitance is only 700 fF, which greatly reduces the total power consumption of the analog frontend circuits. The 12-bit ADC is fabricated using 0.18-μm complementary metal-oxidesemiconductor technology, and it consumes only 26 μW from a 1 V supply at 1-MS/s. The measured signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 60.1 and 72.6 dB, respectively. The measured effective number of bits (ENOB) for a 100 kHz input frequency is 9.7 bits. At the Nyquist input frequency, the measured SNDR and SFDR are 59.7 and 71 dB, respectively. The ENOB is maintained at 9.6 bits and the figure-of-merit is 33.5 fJ/conversion-step.

References

[1] M. D. Scott, B. E. Boser, and K. S. J. Pister, An Ultralow-Energy ADC for Smart Dust, IEEE Journal of Solid-State Circuits, 38 (2003) 1123–1129.10.1109/JSSC.2003.813296Search in Google Scholar

[2] A. O’Driscoll, K. V. Shenoy, and T. H. Meng, Adaptive Resolution ADC Array for an Implantable Neural Sensor, IEEE Trans on Biomedical Circuits and Systems, 5 (2011), 120–130.10.1109/TBCAS.2011.2145418Search in Google Scholar PubMed

[3] Y.-K. Chang, C.-S. Wang, and C.-K. Wang, A 8-bit 500-KS/s Low Power SAR ADC for BioMedical Application, IEEE Asian Solid-State Circuits Conference (A-SSCC) (2008), pp. 228–231.Search in Google Scholar

[4] R. F. Yazicioglu, P. Merken, R. Puers, and C. Van Hoof, A 200μW Eight-Channel Acquisition ASIC for Ambulatory EEG Systems, IEEE International Solid-State Circuits Conference (ISSCC) (2008), pp. 164–165.10.1109/ISSCC.2008.4523108Search in Google Scholar

[5] N. Verma, A. Shoeb, J. Bohorquez, J. Dawson, J. Guttag, and A. P. Chandrakasan, A Micro-Power EEG Acquisition SoC with Integrated Feature Extraction Processor for a Chronic Seizure Detection System, IEEE Journal of Solid-State Circuits, 45 (2010) 804–816.10.1109/JSSC.2010.2042245Search in Google Scholar

[6] N. Verma and A. P. Chandrakasan, An Ultra Low Energy 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Nodes, IEEE Journal of Solid-State Circuits, 42 (2007) 1196–1205.10.1109/JSSC.2007.897157Search in Google Scholar

[7] X. Zou, X. Xu, L. Yao, and Y. Lian, A 1-V 450-nW Fully Integrated Programmable Biomedical Sensor Interface Chip, IEEE Journal of Solid-State Circuits, 44 (2009) 1067–1077.10.1109/JSSC.2009.2014707Search in Google Scholar

[8] G. Promitzer, 12-bit Low-Power Fully Differential Switched Capacitor Noncalibrating Successive Approximation ADC with 1 MS/s, IEEE Journal of Solid-State Circuits, 36 (2001) 1138–1143.10.1109/4.933473Search in Google Scholar

[9] M.-H. Wu, Y.-H. Chung, and H.-S. Li, A 12-bit 8.47-fJ/Conversion-Step 1-MS/s SAR ADC using Capacitor-Swapping Technique, IEEE Asian Solid-State Circuits Conference (A-SSCC) (2012), pp. 157–160.10.1109/IPEC.2012.6522649Search in Google Scholar

[10] Y.-H. Chung, M.-H. Wu, and H.-S. Li, A 24μW 12b 1MS/s 68.3dB SNDR SAR ADC with Two-Step Decision DAC Switching, IEEE Custom Integrated Circuits Conference (CICC) (2013), pp. 1–4.Search in Google Scholar

[11] C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS Process, IEEE Symposium on VLSI Circuits, Digest of technical papers (2009), pp. 237–238.Search in Google Scholar

[12] S.-W. M. Chen and R. W. Brodersen, A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-μm CMOS, IEEE Journal of Solid-State Circuits, 41 (2006) 2669–2680.10.1109/JSSC.2006.884231Search in Google Scholar

[13] C.-C. Liu, S.-J. Chang, G.-Y. Huang, Y.-Z. Lin, C.-M. Huang, C.-H. Huang, et al., A 10b 100MS/s 1.13mW SAR ADC with Binary Scaled Error Compensation, IEEE International Solid-State Circuits Conference (ISSCC) (2010), pp. 368–369.10.1109/ISSCC.2010.5433970Search in Google Scholar

[14] P. Harpe, E. Cantatore, and A. Van Roermund, A 10b/12b 40 kS/s SAR ADC with Data-Driven Noise Reduction Achieving up to 10.01 ENOB at 2.2 fJ/Conversion-Step, IEEE Journal of Solid-State Circuits, 48 (2013) 3011–3018.10.1109/JSSC.2013.2278471Search in Google Scholar

[15] A. Agnes, E. Bonizzoni, P. Malcovati, and F. Maloberti, A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC with Time-Domain Comparator, IEEE International Solid-State Circuits Conference (ISSCC) (2008), pp. 246–247.10.1016/j.humimm.2014.09.009.10.1016/j.humimm.2014.09.009Search in Google Scholar PubMed

[16] M. Yoshioka, K. Ishikawa, and T. Takayama, A 10b 50MS/s 820μW SAR ADC with On-Chip Digital Calibration, IEEE International Solid-State Circuits Conference (ISSCC) (2010), pp. 384–385.10.1109/ISSCC.2010.5433965Search in Google Scholar

[17] J Jin., Y. Gao, and E. Sanchez-Sinencio, An Energy-Efficient Time-Domain Asynchronous 2 b/ Step SAR ADC with a Hybrid R-2R/C-3C DAC Structure, IEEE Journal of Solid-State Circuits, 49 (2014) 1383–1396.10.1109/JSSC.2014.2317139Search in Google Scholar

[18] B. Fotouhi and D. A. Hodges, High-Resolution A/D Conversion in MOS/LSI, IEEE Journal of Solid-State Circuits, SC-14 (1979) 920–926.10.1109/JSSC.1979.1051298Search in Google Scholar

[19] H.-S. Lee, D. A. Hodges, and P. R. Gray, A Self-Calibrating 15 Bit CMOS A/D Converter, IEEE Journal of Solid-State Circuits, SC-19 (1984) 813–819.10.1109/JSSC.1984.1052231Search in Google Scholar

[20] M. Trakimas and S. R. Sonkusale, An Adaptive Resolution Asynchronous ADC Architecture for Data Compression in Energy Constrained Sensing Applications, IEEE Trans on Circuits and Systems I, 58 (2011) 921–934.10.1109/TCSI.2010.2092132Search in Google Scholar

[21] S. Kundu, J. H. Lu, E. Alpman, H. Lakdawala, J. Paramesh, B. Jung, et al., A 1.2 V 2.64 GS/s 8 bit 39 mW Skew-Tolerant Time-interleaved SAR ADC in 40 nm Digital LP CMOS for 60 GHz WLAN, IEEE Custom Integrated Circuits Conference (CICC) (2014), pp. 1–4.10.1109/TCSI.2015.2452372Search in Google Scholar

[22] X. Y. Tong, Z. M. Zhu, Y. T. Yang, and L. X. Liu, D/A Conversion Networks for High-Resolution SAR A/D Converters, Electronics Letters, 47 (2011) 169–171.10.1049/el.2010.3469Search in Google Scholar

[23] B. D. Smith, Coding by Feedback Methods, Proceeding of the IRE (1953), pp. 1053–1058.10.1109/JRPROC.1953.274323Search in Google Scholar

[24] P. Harpe, C. Zhou, Y. Bi, N. P. Van der Meijs, X. Wang, K. Philips, et al., A 26μW 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios, IEEE Journal of Solid-State Circuits, 46 (2011) 1585–1595.10.1109/JSSC.2011.2143870Search in Google Scholar

[25] M. Miyahara, Y. Asada, D. Paik, and A. Matsuzawa, A Low-Noise Self-Calibrating Dynamic Comparator for High-Speed ADCs, IEEE Asian Solid-State Circuits Conference (A-SSCC) (2008), pp. 269–272.10.1109/ASSCC.2008.4708780Search in Google Scholar

[26] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, Matching Properties of MOS Transistors, IEEE Journal of Solid-State Circuits, 24 (1989) 1433–1440.10.1109/JSSC.1989.572629Search in Google Scholar

[27] M. Dessouky and A. Kaiser, Very Low-Voltage Digital-Audio ΣΔ Modulator with 88-dB Dynamic Range Using Local Switch Bootstrapping, IEEE Journal of Solid-State Circuits, 36 (2001) 349–355.10.1109/4.910473Search in Google Scholar

[28] R. H. Walden, Analog-to-Digital Converter Survey and Analysis, IEEE Journal on Selected Areas in Communications, 17 (1999) 539–550.10.1109/49.761034Search in Google Scholar


The authors thank the National Chip Implementation Center for its support in the chip implementation. This research was supported by the Ministry of Science and Technology of Taiwan, R.O.C. (Grant MOST 101-2218-E-011-044-MY2).


Published Online: 2016-4-30
Published in Print: 2018-1-26

© 2018 Walter de Gruyter GmbH, Berlin/Boston

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