A synaptic device built in one diode–one resistor (1D–1R) architecture with intrinsic SiO_x-based resistive switching memory

1 Introduction

In recent years, resistive random access memory (ReRAM) has drawn much interest as a promising candidate for next-generation nonvolatile memory (NVM) due to its potential scalability beyond 10 nm feature size using a crossbar structure, fast switching speed, low operating power, and good reliability [1–3]. Traditional charge-based NVM typically includes a charge “trapping layer” within a transistor configuration that requires a high thermal budget and large footprint (typically 6F², where F = minimum feature size) [4, 5]. Resistive switching (RS) memory operates by controlling device resistance with an external electrical manipulation [6–9], leading to better electrical performance, smaller design area (4F²), and excellent cycling endurance [10]. Based on the 2013 International Technology Roadmap for Semiconductors (ITRS), ReRAM is one of two recommended candidate technologies for emerging memory devices [11]. Also, resistive-based memories represent a new class of devices compatible with applications that go beyond traditional electronics configurations, for example, three-dimensional (3D) stacking, nanobatteries, neuroelectronics and Boolean logic operations [12–17].

Neuroelectronics and synaptic electronics are interesting applications for ReRAM that aim to build artificial synaptic devices that emulate the computations performed by biological synapses [15, 18–22]. These emerging fields of research have potentially better efficiency in solving complex problems and outperform real-time processing of unstructured data than conventional von Neumann computational systems [23]. There have been many studies of binary metal oxide-based and perovskite oxide-based resistance switching characteristics for synapse-like electronic device development [24, 25], which can have operating instability issues due to difficulty in controlling stoichio-metric compositions [26, 27]. Therefore, a simple process that is compatible with conventional complementary metal-oxide semiconductor (CMOS) fabrication allows multilayer compositional engineering and provides good electrical stability and high yield, which are critical requirements for neuroelectronics realization [28]. Silicon oxide (SiO_x) has long been used as gate dielectrics for metal-oxide-semiconductor field-effect transistors. In addition to excellent insulating properties, resistive switching properties have been observed in SiO_x materials as early as 1962 by Hickmott and 1967 by J. G. Simmons and R. R. Verderber, with additional modeling being done by G. Dearnaley in the 1970s [29–31]. They observed that a simple metal-insulator-metal structure (e.g., Au/SiO_x/Al, MIM) can form an active memory device based on its repeatable negative resistance phenomenon. Recently, Yao et al. have reported SiO_x-based resistive switching behaviors in vacuum, indicating that this traditionally passive material can be converted to an active memory element and controlled by external electrical activation [32–37]. The amount of recent reports also describe and indicate using SiO₂ as the active switching medium in resistive switching memory devices [38–41]. We have further demonstrated a Si diode (1D) with low reverse-bias current integrated with a SiO_x-based memory element (1R) using nanosphere lithography and deep Si etching to pattern a P⁺⁺/N⁺/N⁺⁺ epitaxial Si wafer [42]. The above achievements for intrinsic SiO_x-based ReRAM indicate: (1) high device yield, forming-free operation, reduced operating voltage, excellent scalability (to dimensions < 40 nm in 1D–1R architectures without sacrificing the device performance, such as the retention of multilevel states and endurance reliability) and good device stability; (2) pulsed programming in the 50 ns-regime and low reverse current with large rectification ratio to meet low-energy consumption criteria (> 10⁶ for high-conductance states and negative-bias current) for integrated 1D–1R nanopillar architectures; and (3) wide programming resistance dynamic range (potentially up to 10⁸), multilevel states, and excellent reliability. However, the resistive switching mechanisms in SiO_x are not well understood, and use as an electronic synaptic device has not previously been demonstrated.

In this work, SiO_x-based resistive switching memory elements (1R) are integrated with Si diodes (1D) using conventional CMOS processing to demonstrate a 1D–1R device with synaptic behaviors. The Si diode provides low reverse-bias current and high-power efficiency for future neuromorphic computing array architectures. Unlike other binary or complex metal oxide materials [43–46], SiO_x has been used in CMOS manufacturing for over 50 years due to its excellent electrical isolation properties, low-cost, high chemical stability, compatibility with mainstream integrated circuit materials, high-throughput processing and large-area production using chemical vapor deposition (CVD). A 1D–1R architecture fabricated at the wafer-scale using conventional CMOS processing can therefore be well-controlled in thickness, size, and electrical characteristics by precisely controlling the doping levels of the diode layers and the temperature and flow-rate of the oxide CVD process [47]. Synaptic device performance is characterized in a prototype 1D–1R array configuration. Robust biological synaptic behaviors such as long-term potentiation (LTP), long-term depression (LTD), and spike-timing dependent plasticity (STDP) are demonstrated with excellent uniformity, low operational variability, and good suppression of static power consumption [43–46]. A bio-inspired proton exchange resistive switching model is used to help characterize this novel application for SiO_x materials. The SET transition in the resistive switching memory is modeled as hydrogen (proton) release from the (SiH)₂ defect to generate a conductive hydrogen bridge, and the RESET transition is modeled as an electrochemical reaction (proton capture) that re-forms nonconductive (SiH)₂. The synaptic behaviors exhibited by the 1D–1R device demonstrates good potential for using a simple and robust approach for large-scale integration of programmable neuromorphic chips using CMOS technology.

2 Experiment

Devices were fabricated at XFAB Inc. in Lubbock, TX. Secondary electron microscopy (SEM) images show a top-down view of a 1D–1R test structure (Figure 1(a)), a tilted (45°) view of the 1R device (Figure 1(b)) and a cross-section image of the 1R device showing layer information (Figure 1(c)). The 1R device was fabricated by implanting the Si substrate to form an n-type lower electrode. The active SiO_x memory layer was then deposited to a thickness of 40 nm using plasma-enhanced chemical vapor deposition (PECVD) with proper thickness-dependence resistive switching optimization. An n-type polysilicon layer was deposited onto the SiO_x layer to form the top electrode. An opening in the polysilicon layer was made after all thermal oxidation and implant anneal steps were complete (Figure 1(b)). A first dielectric layer was then deposited over the polysilicon top electrode. Tungsten plugs were used to make electrical contact to the n-type Si lower electrode and the polysilicon top electrode. After all the back-end dielectrics and a passivation layer were deposited, the back-end dielectric layers were removed using reactive ion etch (RIE) to the Si substrate. This RIE step cleared out the SiO_x layer inside the hole, and created a SiO_x sidewall where the memory device is formed (Figure 1(c)). Polymer residue that remained after the post-RIE cleaning steps was removed by a 30-second buffered oxide etch (BOE). The pn diode used in the 1D–1R test structures was formed by an implanted p-well inside a deep n-well, and is a standard device available from XFAB with 40 V reverse-bias breakdown voltage, 1 nA reverse-bias leakage current, and 0.5 V forward voltage. The dimension for 1R device is 2×2 μm and for 1D device is 20×20 μm. A Lake Shore Cryotronics vacuum probe chamber (< 1 mTorr) and Agilent B1500A device analyzer were used to electroform devices and measure the DC/ACI-V response. The SET process programs the device to a conductive, low-resistance state (LRS). The RESET process programs each device to a low-conductance, high-resistance state (HRS). A Kratos Axis Ultra HSA X-ray Photoelectron Spectrometer (XPS) equipped with a monochromatized aluminum x-ray source was used to analyze several SiO_x materials deposited in our laboratory using different methods. Calibration of the binding energy scale was set by fixing the C-(C, H) peak at 284.4 eV. Figure 1(d) shows XPS analysis results for the O-1s and Si-2p binding energies in thermal oxide grown by low-pressure chemical vapor deposition (LPCVD) and PECVD oxide. The existence of stoichiometric SiO₂ can be observed in thermal oxide (binding energy Si: 103.2 eV; O: 532.5 eV) with essentially no sub-oxide bonding being detected. In contrast, the PECVD oxide has nonstoichiometric SiO_x (x is about 0.93 based on the peak position and orbital valence) composition in the switching layer, as indicated by the peak binding energies in the XPS spectra (Si: 530.5 eV; O: 101.9 eV and 100.9 eV) [48–50], which may promote low-energy defect generation during the electroforming process.

Fig. 1a

Top-down SEM image of 1D–1R architecture. (b) Tilted top-down SEM image of resistive memory device. (c) SEM cross-section image showing metal contact to polysilicon top electrode, metal 1 (M1) and metal 2 (M2) layers, and polysilicon/SiO₂/Si 1R device. (d) Si-2p_2/3 and O-1s XPS spectra for PECVD oxide and thermal oxide.

3 Results and discussions

Figure 2(a–d) shows I-V characteristics for DC voltage sweeps applied to the SiO_x-based 1D–1R devices fabricated by the conventional CMOS process. Voltage was applied to the 1D top electrode (p-type Si) with bottom 1R electrode (n-type Si) at ground. All testing was done in vacuum. To establish reversible resistive switching in each SiO_x-based 1R ReRAM device, a forward/backward voltage sweep (Figure 2(a)) was used to electroform a conductive filament, where current is observed to increase dramatically at 22.5 +/– 2.9 V during the forward voltage sweep. Electroforming is completed during the backward voltage sweep from the maximum sweeping voltage to 0 V, resulting in a LRS. After electroformation, resistive switching performance of 1D–1R is stabilized by cycling the device multiple times using voltage sweeps (Figure 2(b)). The SET process is a 10 V forward/backward sweep without any compliance current limit (CCL) to program the device to the LRS. The RESET process is done by sweeping the voltage to 17 V, where current decreases as the voltage is swept from about 10 V to 17 V; and the device is programmed into a HRS. The HRS/ LRS resistance ratio is at least ~10³ at 1 V bias, which satisfies sensing requirements [3, 51]. For diode characteristics, the forward current can reach 100 mA at 2 V, which indicates a forward current level high enough to support the RESET process. The reverse current is below 1×10^–12 A at –5 V. Compared with Schottky diodes, the advantages of Si-based PN diodes include low reverse-current, high reverse-bias breakdown voltage, and fewer stability issues. The quality of the Si-based PN diode can dramatically affect diode reverse or forward current characteristics, as well as power consumption (describe below). Also, the chosen Si-based PN diode configuration has high reverse breakdown voltage (> 40 V), which is important for SiO_x-based ReRAM operating in an array. Figures 2(c) and 2(d) demonstrate the gradual change of resistive states by modulating the voltage sweep range during the SET and RESET process, respectively. Specifically, SET and RESET voltages were changed from 3.5 V to 9.5 V in 0.5 V increments and from 11 V to 18 V in 0.5 V decrements, respectively, thus potentially enabling multilevel programming in a single memory cell. It may be noted that the electroforming voltages measured here (~28 V) are somewhat higher than those measured in previous work on metal-oxide-semiconductor device architectures or nanopillar type 1D–1R architectures [30, 32], which may be due to fewer electrically active defects being near the SiO_x sidewall as a result of the fabrication process. For example, several high temperature steps (> 650 °C) were done after PECVD SiO₂ deposition, namely: polysilicon deposition, thermal oxidation, and implant anneals, which might densify the SiO₂ layer, reduce the as-deposited defect levels, increase the soft breakdown threshold, and thus increase the filament formation energy during the subsequent electroforming process. Interestingly, the RESET voltage (the voltage at which LRS current begins to decrease) is greater than or equal to the SET voltage (where HRS current increases sharply), which is possibly a unique characteristic in SiOx-based ReRAM as compared to other materials systems [25, 52]. The difference between RESET and SET voltages can potentially be controlled by optimizing the series resistance in the circuit and choice of electrode materials [53]. The switching voltage is independent of device scalability and SiO_x thickness reduction. Figure 2(e) shows multilevel retention performance of SiO_x-based 1D–1R devices obtained by controlling the maximum SET voltage from 3 V to 9 V. The readout current of LRS and HRS is measured at 1 V every 60 seconds after each programming operation. The retention reliability test demonstrates multilevel operation by using different SET voltages, and no degradation is observed for more than 10³ seconds, thus confirming the stable, nonvolatile nature of the SiO_x-based 1D–1R devices. In recent studies, a possible proton-exchange model consistent with the observed resistive switching I-V response has been proposed, as shown in Figure 2(f) [53–55]. Several studies have used transmission electron microscopy (TEM) to document the presence of Si nanocrystals within the CF [32, 35, 56], but it is not yet clear whether resistive switching (RS) is the result of an overall increase in nanocrystal size or whether switching occurs in “GAP” regions in between nanocrystals. Most models of ReRAM switching involve the drift or diffusion of O²⁻ ions (or oxygen vacancy defects) [28], but these models cannot explain the I-V response (such as backward scan effect, as shown in Figure 2(a)) or the ambient effects on resistive switching observed in the SiO_x device [57, 58]. The models used to describe the possible SiO_x-based RS mechanisms differ from most conventional models by considering that the defects responsible for RS may remain localized within the switching region so that resistive switching occurs when a collection of defects are driven between conductive and nonconductive forms [58]. Based on the reported electrical and structural properties of known SiO_x defects [53], it has been further understood how the possible proton exchange reactions can dramatically alter the conductivity of specific defects, leading to a model description where the LRS has a large concentration of conductive defects within the switching region, and, conversely, when the device is programmed to the HRS, most of the defects are converted to their nonconductive form. The electrically conductive hydrogen bridge (Si-H-Si) is viewed as the most likely defect responsible for the LRS due to its shallow defect level below the conduction band for electron transport, and the trigger-voltage from HRS to LRS is close to the activation energy of defect transformation ([SiH]₂ to Si-H-Si) [53, 54]. Electrochemical reactions that form the nonconductive (SiH)₂ defect are discussed as potential mechanisms that enable localized switching without incorporating ion diffusion or drift mechanisms into the model. The transitions between HRS and LRS are modeled as being initiated by hydrogen desorption from (SiH)₂ to form Si-H-Si, and as electron injection into a fixed positive-charge defect that induces proton release and an electrochemical reaction with Si-H-Si to re-form (SiH)₂, respectively. The RS model not only provides insights into multilevel operational characteristics but also implies a possible biomimetic chemical reaction similar to reactive oxygen species (ROS–like) production for future device characterizations [59–61].

Fig. 2

DC sweep resistive switching behaviors of 1D–1R architecture: (a) Forward/backward voltage sweeps during electroforming process averaged for 256 devices in a 16×16 array (grey curves). (b) 10 I-V resistive switching SET/RESET cycles. The inset shows the average of 100 measurement cycles of diode I-V behavior. (c) Effects of voltage modulation on I–V curves in SET process plotted on linear-scale and log-scale (inset). (d) Effects of voltage modulation on I–V curves in RESET process plotted on log-scale. (e) Retention measurement results of multistate programming obtained by controlling the SET voltage. (f) Proton exchange induced resistive switching model and defect transitions.

Figures 3(a–h) show contour plots of the current-change ratio achieved by modulating the AC pulse height and pulse width applied to 1D–1R devices for both SET and RESET switching events, leading to optimized waveform designs for a biological synaptic device. The current-change ratio is defined as log₁₀(I_FINAL/I_INITIAL), where I_INITIAL and I_FINAL are the currents measured at 1 V before and after applying the programing waveform, respectively. The SET switching events (S) increase current through the device, leading to positive current change ratios, whereas RESET switching events (R) decrease device current and lead to negative current change ratios. The pulse mappings are generated using the Agilent B1500A device analyzer in a three-step process: (1) Initial states are programmed using a fixed DC voltage before the pulse waveform is applied (see Figure 4 for the detailed state mapping procedure); (2) The pulse waveform is applied; and (3) Device state is read by measuring the current at 1 V before and after each pulsed switching event. One can observe by inspecting the contour lines in Figure 3 that when larger pulse heights (higher voltages) are applied to the device, shorter pulse widths are needed to achieve a similar current-change ratio. In general, we find that a single 1R device operates at higher speed and requires lower programming voltages as compared to a 1D–1R device [62]. The higher operating voltages and lower operating speed of the integrated 1D–1R device may result from higher parasitic resistance in the Si electrodes, their contacts and the diode, as well as higher parasitic capacitance in the diode, all of which can act to degrade the pulse mapping results shown in Figures 3(a) and 3(b). It should be noted that current sneak-path issues in arrays of 1R devices would cause misread problems and substantially increase standby power consumption. The 1D–1R devices are used to suppress sneak-path currents, and perform much better than 1R devices in an array architecture. From Figures 3(a) and 3(b), it can be calculated that the switching energies to achieve at least a one-order-of-magnitude change in resistance in the 1D–1R architecture are about 0.01 pJ for SET and 1.54 nJ for RESET operations. However, due to the suppression of sneak-path current, the standby power during a 1 V read operation can be dramatically reduced in 1D–1R devices (1 pW) as compared to 1R devices (1 μW). Minimizing the total power consumption by sneak-path issue is as crucial as reducing the synaptic dissipation.

Fig. 3

AC pulse mapping contour plots of current-change ratio by modulating pulse height and pulse width to demonstrate synaptic behaviors in 1D–1R architectures: (a) SET (S) and (b) RESET (R) mapping results of 1D–1R device. (c) and (e) Long-term potentiation (LTP). (d) and (f) Long-term depression (LTD) using the identical pulse method as a function of pulse width. (g) and (h) LTP and LTD are shown using the nonidentical pulse method as a function of pulse width, respectively. “S” and “R” denote the increment/decrement of current state changes after applying the AC pulse (defined as Log₁₀; (I_FINAL/I_INITIAL), where I_FINAL/I_INITIAL is current ratio measured at 1 V after/before the pulse is applied.

Most importantly, the pulse mapping results not only demonstrate the potential for multilevel programming by properly designing the pulse waveforms for SET and RESET operations, but also demonstrate the potential to realize biological synaptic behaviors. Figures 3(c)–(h) demonstrate the optimization waveform design for biological synaptic behaviors in 1D–1R SiO_x-based resistive switching memories. The long-term potentiation (LTP)/long-term depression (LTD) are a long-lasting enhancement/reduction in signal transmission between two neurons, which can be realized by designing the SET and RESET pulse waveform to use either identical (fixed pulse width and pulse height, as shown in Figures 3(c)–(f)) or nonidentical (variable pulse width or pulse height, as shown in Figures 3(g) and 3(h)) pulsing methods. Both methods can be used to demonstrate a SiO_x-based synaptic device. It may be noted that when the dynamic range was evaluated in detail and the tradeoffs between high dynamic range and gradual multilevel programming performance (Figures 3(e)–(h)) were considered, it was found that nonidentical pulse waveform methods may have certain advantages. (Dynamic range is defined as the maximum achievable resistance of the HRS divided by the minimum resistance of the LRS.) Although nonidentical pulsing might require a more complex neuromorphic circuit, our results show that this approach enables more efficient programming to target states while maintaining a larger dynamic range (Figures 3(g)–(h)). The use of nonidentical pulse heights ranging from 4 V to 10 V in 0.3 V increments (for LTP) and ranging from 11 V to 17 V in 0.3 V decrements (for LTD) allow the dynamic range to be mapped for pulse widths ranging from 100 ns to 1 ms, thereby realizing biological synapse behaviors in the SiO_x-based 1D–1R architecture (Figures 4(g)–(h)). The switching energy is defined as I×V×δt, where δt is the pulse width. For δt = 100 ns, the smallest switching energies are ~6 fJ and ~130 pJ for LTP and LTD, respectively. The larger energy for LTD is mainly due to the lower resistance of the LRS (~93 kΩ) compared to the HRS (~ 260 MΩ), which results in higher current (118.28 μA) for the RESET process than for the SET process (15.38 nA). In order to minimize synaptic energy consumption, all three components–programming current (~nA level switching), pulse amplitude (< 1 V), and programming time (< 10 ns)–need to be minimized. In SiO_x-based ReRAM and other material systems, an exponential voltage–time relationship is commonly observed [63, 64]. A small increase in programming voltage will decrease programming time exponentially. Hence, low programming energy is obtained by minimizing the programming time (traded off by increasing the pulse amplitude slightly) for ReRAM. Further decrease in synaptic energy consumption in switching process to fJ levels will be challenging but important to build very large-scale systems [65].

Fig. 4

The sequential procedures of pulse mapping for device characterizations. Each circulant matrix represents a loop of pulse height mapping. The stability of DC initialized states are confirmed, as shown in (b) for 1R and 1D–1R architectures (c–d) AC pulse mapping contours achieved by modulating pulse height and pulse width: (c) SET and (d) RESET mapping results of 1R device.

Such flexible artificial control built with synaptic devices could provide a suitable platform for a broad range of computing applications, as shown in Figure 5. Some of the advantages that SiO_x-based synaptic devices provide over other resistive switching materials include a higher dynamic range (~10⁴) [51] and the potential to achieve as many as 60 multilevel states in both LTP and LTD by changing the increment/decrement of the voltage step, as shown in Figure 5 (a). These advantages may arise as the result of there being a large number of defects within the switching region of the memory device. Switching is modeled as a change in conductivity of a group of defects within the switching region. In this framework, defects are not created or destroyed, but are simply driven between conductive and nonconductive forms by proton exchange reactions that are known to occur in SiO_x materials (Figure 2(f)) [54, 66–104]. The SET and RESET switching transitions can be described in more detail with the aid of the electron energy band diagrams shown in Figure 5(b), which were constructed using the thermodynamic and switching charge-state energy levels reported by Peter Blochl in 2000 [104]. The ideal energy band diagrams in Figure 5(b) represent only a single electron pathway through the memory device, whereas in reality there are likely many such percolation pathways in parallel. The SET transition is modeled as being the result of trap-assisted electron tunneling through (SiH)₂ defects that stimulates H desorption and reaction of H⁺ with absorbed water (SiOH)₂ to form conductive Si-H-Si and H₃O⁺ (Figure 2(f)). Trap-assisted tunneling can only occur when the bias across the switching region is ≥2.6 V, which is the effective band gap of the (SiH)₂ defect and compares well with the observed minimum SET voltage of ~2.5 V in the I-V response [53, 54]. The RESET transition is modeled as being the result of Fowler-Nordheim electron tunneling into the H₃O⁺ defect to stimulate proton release and electrochemical reactions that re-form (SiH)₂ and (SiOH)₂ (Figure 2(f)). More detailed explanations of the defect energy levels and effective bandgaps are provided in Table 1. The band diagrams shown in Figure 5(b) are found to be consistent with measured electron energy barriers [54] and electroluminescence results reported for similar devices [56].

Fig. 5

Demonstration of a SiO_x-based synaptic device. (a) Sequential LTP/LTD behaviors as a function of increment/decrement voltage steps (0.1 V, 0.2 V, and 0.3 V) by nonidentical pulse form. (b) Energy band diagrams: For HRS and SET process, showing theoretical bandgap of (SiH)₂ defect within gap region of length IGAP, theoretical bandgap of Si-H-Si defects outside the gap region, and trap-assisted-tunneling SET transition (green arrow). Barrier height to electron transport is f ~0.8eV. For the LRS and RESET process, showing theoretical bandgap of Si-H-Si, H₃O⁺ energy level, switching region of length ISW, and Fowler-Nordheim tunneling RESET transition (red arrow). (c–d) A pulse waveform design using the nonidentical pulsemethod for demonstration of spike-timing-dependent plasticity (STDP) as a function of spike pulse width intervals. (e–f) A demonstration of spike-timing-dependent plasticity (STDP) using the nonidentical pulsemethod with different spike widths.

Figures 5(c)–(f) demonstrates spike-timing-dependent plasticity (STDP) in the SiO_x-based 1D–1R architecture, which is a biological process that adjusts the strength of connections between two neurons in a synapse gap junction region that is an electrically conductive link between the pre- and post-synaptic neurons. Two pulse generator sources are built to simulate the pre- and post-synaptic neurons, which provide the pulse waveforms using the nonidentical pulse method for demonstration of spike-timing-dependent plasticity (STDP). By design of pre-neuron and post-neuron spikes in neuromorphic circuits, the strength of the conductance change can be modulated based on the delta spike timing (Δt) between the two neurons (Figures 5(c)–(d)). Figures 5(e)–(f) demonstrates a total of 10 different states of STDP biological behavior for depression and potentiation with n = 2, 4, 6, 8, 10 and as a function of spike width modulation, ranging from 100 ns to 1 ms. For example, the depression of conductance change strength can be achieved by using multistep spike heights from –4 V to 0 V in the pre-neuron state and a single spike height fixed at 13 V in the post-neuron state, with both neurons having a fixed pulse width of 10 μs and a firing period of 20 μs, as shown in Figures 5(e)–(f). When the time delay difference is –10×(n–1) μs, where n is an even number, the total spike waveform (post-neuron spike minus pre-neuron spike) applied to the synapse gap junction region can adjust the conductance ratio between two neurons over the range from 10^–3 to 0.1 in the depression direction (RESET process) as compared with the initial LRS conductance (Figure 5(f)). Similarly, the potentiation of conductance change strength can be achieved by using multistep spike heights from 4 V to 8 V in the pre-neuron state and a single spike height also fixed at 13 V in the post-neuron state, with both neurons having a fixed pulse width of 10 μs and a firing period of 20 μs. When the time delay difference is 10 (n–1) μs, where n is an even number, the total spike waveform (post-neuron spike minus pre-neuron spike) applied to the synapse gap junction region can in this case adjust the conductance ratio between neurons over the range from 10³ to 0.01 in the potentiation direction (SET process) as compared with the initial HRS conductance (Figure 5(e)). It may be noted that the 1D–1R architecture not only avoids sneak-path issues and lowers standby power consumption, but also helps to realize STDP behaviors. Without the 1D rectification characteristics in reverse-bias polarity, the above spiking forms cannot be implemented due to the unipolar nature of the 1R device, specifically in the potentiation behaviors under negative bias. In the 1R case, an applied voltage above the RESET threshold voltage (for example, –9 V) can trigger the RESET process and induce depression behaviors instead of potentiation behaviors. Also, for depression behaviors, when the time delay difference is smaller than the spiking width, the remaining 4 V spike height in this case would not fire the synapse towards a LRS in the depression direction (see Figure 3(h)). Therefore, by carefully designing the firing pulses between neurons in the neuromorphic circuit, a biological synapse behavior can be demonstrated with 1D–1R SiO_x-based resistive switching memories.

Figure 6 shows robust electrical reliability and low variation in a 1D–1R-array structure that can potentially be used in future neuromorphic computing applications. Figure 6(a) shows a portion of a test chip containing a 16×16 bit cell array. Each bit cell is comprised of a Si PN diode isolation element and a SiO₂-based resistive memory element. Electroforming yield of the 256 bit cells in the array was 98%. Of these yielding devices, 100% passed a quick, 10-cycle switching performance test without failure. Figure 6(b) shows the average and ± 3-sigma variation of resistive switching behaviors in the 16×16 bit cell array cycle using a 10 V double-sweep for SET and 20 V single-sweep for RESET. In this case, the 3-sigma LRS/HRS current ratio at 1 V read bias was at least 6×10³. A gradual change in the SET transition is observed over the voltage range from 3.5 V to 6 V, thus allowing programming of the multilevel states that are required for a robust neuromorphic circuit design, and which are accompanied by excellent sub-μs transitions with at least ×10 resistance ratio after 10⁵ cycles (Figure 6(c)). A 2×2 array of integrated 1D–1R bit cells with unipolar programming strategy shows excellent write/read disturbance immunity after 10⁶ pulses for unselected devices and a clear programming window > 100 (Figure 6(d)). In addition to 1D–1R device arrays, the hybrid CMOS/synaptic device architecture shown in Figure 6(e) has been successfully demonstrated as shown in Figure 6(f) by the I-V resistive switching plots. The 1D–1R architecture with SiO_x-based resistance switching devices and the structure of artificial neural networks map naturally onto hybrid CMOS/synapse circuits that can be designed on a single chip (Figure 7) to provide predictable results with an ultimate scaling potential of CMOS technology to the sub-10-nm level, which could possibly challenge the complexity and connectivity of the human brain.

Fig. 6

Electrical variation and reliability results for array structure for potential use in future neuromorphic computing applications. (a) Optical image of a 16×16 bit cell array test chip. (b) Averaged data for 256 bit cells, with each bit cell programed using 10 SET/RESET cycles immediately after electroforming. (c) 100 k SET-RESET cycles achieved under AC bias conditions (SET: 9 V, 100 ns; RESET: 15 V, 500 ns; READ: 1 V, 1 μs) in 1D–1R architecture. (d) Writing/ Reading disturbance of unselected device under worst-case conditions (“1/2 bias” scheme). (e) Optical image of a PMOS-1D–1R-NMOS test structure and circuit schematic. (f) DC sweep resistive switching behaviors of CMOS-1D–1R architecture.

Fig. 7(a)

Bio-inspired and mixed-signal information processing: hybrid CMOS/ReRAM circuits may also enable efficient analogue dot-product computation, which is a key operation in artificial neural networks and many other information processing tasks. (b) A fabricated 8×8 artificial neural network array combined with CMOS transistors and logic control.

4 Summary

In summary, we have demonstrated potentiation, depression, and spike timing dependent plasticity in a synaptic device built using a SiO_x-based 1D–1R architecture. Proton-induced resistive switching behaviors in the SiO_x memory element were discussed, where the SET threshold is modeled as proton desorption from the (SiH)₂ defect to generate the conductive hydrogen bridge, Si-H-Si, and the RESET transition is modeled as proton release and capture to re-form nonconductive (SiH)₂.The electrical results demonstrate that the technology has good potential for providing a simple and robust approach for large-scale integration of programmable neuromorphic chips using CMOS technology, and represent a critical milestone regarding the potential use of SiO₂-based resistive memory as a synaptic device in future synthetic biological computing applications.