Mach–Zehnder interferometer-enabled optical flip-flop for photonic memory applications
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Rakesh Kumar
Abstract
Semiconductor optical amplifiers (SOAs) play a crucial role in various applications, including optical networks, optical tomography, and optical logic systems. High-speed performance is particularly essential for applications in optical networks and logic circuits. SOA-based Mach–Zehnder interferometers (SOA-MZIs) have been widely utilized to demonstrate all-optical Boolean operations such as XOR, OR, AND, and NOR. A rate equation model for SOA-MZIs has been developed to analyze key optical logic devices, including the J-K Flip Flop. Simulation results indicate that these flip-flop circuits can operate efficiently at high speeds. Additionally, optical pseudo-random bit stream (PRBS) generators are vital for all-optical encryption systems. This study provides an in-depth discussion on the design principles, theoretical analysis, and experimental validation, demonstrating its potential for future high-performance optical computing applications having extinction ratio 25.08 dB, quality factor 55.30 dB and Optical cost of 6 unit.
Acknowledgments
We sincerely acknowledge Optiwave Software for providing powerful simulation tools that greatly facilitated our research. The comprehensive features and user-friendly interface of OptiSystem enabled efficient design and analysis of optical communication systems. We are grateful for the support and innovation that Optiwave brings to the photonics and optical engineering community.
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Research ethics: This research on the “Mach–Zehnder Interferometer-Enabled Optical Flip-Flop for Photonic Memory Applications” was conducted with strict adherence to established ethical guidelines. All simulations and analyses were performed using licensed software tools, ensuring the authenticity and reproducibility of results. The authors affirm that this work is original, free from plagiarism, and has not been submitted elsewhere.
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Informed consent: Not applicable.
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Author contributions: Kamal Kishor Upadhyay led the conceptualization, methodology design, and overall supervision of the project. Bharat Bhushan Sharma contributed to system modeling and simulation analysis. Rakesh Kumar and Ritesh Jaiswal assisted in result validation and performance evaluation. Priyansh Pal and Prachi Singh were responsible for data collection, graphical representation, and documentation. Samarth Bhardwaj contributed to literature review and manuscript preparation. All authors reviewed and approved the final version of the manuscript.
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Use of Large Language Models, AI and Machine Learning Tools: None declared.
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Conflict of interest: The authors declare that there are no competing interests related to the publication of this research. All authors have reviewed the manuscript and approved its submission. No financial, personal, or professional relationships have influenced the outcomes or interpretations presented in this study.
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Research funding: This research received no specific grant from any funding agency in the public, commercial, or not-for-profit sectors. The work was carried out using institutional resources provided by the Department of Electronics and Communication Engineering, JSS Academy of Technical Education, Noida, U.P, India.
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Data availability: Not Applicable.
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