A new 9-level quadruple boost inverter for grid integration
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S. V. Kishore Pulavarthi
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Nakka Jayaram
Abstract
This paper presents a novel reduced switch multilevel inverter based on switched capacitor technique for grid integration. It generates nine-level output voltage waveform with only 10 switches. It is suitable for high gain applications since it has a boosting ability of four times. Another feature is that the capacitors have built-in self-voltage balancing. The level shifted pulse width modulation (LSPWM) technique is used to explore the performance of the proposed topology. To determine its optimal performance, the suggested topology is compared to the state-of-the-art topologies in the literature. Simulation of the proposed topology is done under different parameter variations. Further, the thermal design of the proposed topology is done using PLECS software to find the efficiency. Finally, the hardware prototype is implemented using dSPACE 1104 controller to verify its performance.
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Research ethics: Not applicable.
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Informed consent: Not applicable.
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Author contributions: The authors have accepted responsibility for the entire content of this manuscript and approved its submission.
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Use of Large Language Models, AI and Machine Learning Tools: None declared.
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Conflict of interest: The authors state no conflict of interest.
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Research funding: None declared.
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Data availability: Not applicable.
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