Phase Locked Loop Based Techniques for Compensation of Voltage Based Power Quality Issues in Distribution System
-
Sabha Raj Arya
,
Rakesh Maurya
Abstract
This article describes the comparison of different phase locked loops (PLLs) based control algorithms for removal of voltage based power quality problems such as voltage sag/swell, distortions and unbalances etc. For this purpose, Dynamic Voltage Restorer (DVR) is designed with heuristic optimization technique called Multi-objective Grey wolf Optimizer (MOGWO) for PI gains calculation. Three PLLs namely adaptive transfer delay phase locked loop (ATD-PLL), multi complex coefficient filter phase locked loop (MCCF-PLL), and multi synchronous reference frame phase locked loop (MSRF-PLL) are implemented for the control of DVR in a three-phase system. These PLLs are employed for compensation of distortions and imbalances in supply along with voltage sag/swell. Basically, estimation of fundamental and positive sequence components are the basic function of these PLLs that is used for further extraction of reference load voltage. The optimization approach has been implemented for estimation of proportional integral (PI) gains of dc bus as well as ac bus in the system. This approach of tuning PI controller-gains reduces the time by integrating the fixed sized external archive to the GWO for saving and retrieving optimal solutions. Three wires DVR with developed control algorithms are implemented using MATLAB/Simulink and tested in a laboratory environment. The recorded results show satisfactory performance of DVR for compensation of voltage based power quality problems.
Funding statement: Under Science and Engineering Research Board -New Delhi Project (Extra Mural Research Funding Scheme), Grant No. No.SB/S3/EECE/030/2016, DATED 17/08/2016
Appendix
System parameters: AC grid- 415 V, 50 Hz; Load of 15 kVA, 0.85 p.f. (Lagg.); vs (with sag) = 0.7*240 = 168 V; iL = 20.868 A; kVA (transformer) = 3*171.39*20.868/1000 = 10.729 kVA ≈ 11 kVA, 200/100 V; Vdc = 300 V; Cdc = 3300 µF; Interfacing or filter inductor (Lf) = 1.5 mH; Rf = 6 Ω; Cf = 10 µF; dc-PI controller gains: kp1 = 11.51, ki1 = 0.3291, terminal voltage-PI controller gains: kp2 = 29.6530, ki2 = 2.6778; Switching frequency of VSC: (fs) = 5 kHz.
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Articles in the same Issue
- Research Article
- Simulation of Modified Flyback Snubber Circuit for Isolated Bidirectional DC-DC Converter
- Design of Cost Effective Solar PV Powered SRM Driven Agriculture Pump Using Modified Buck-Boost Converter
- High Step-Up Boost Converter with Neural Network Based MPPT Controller for a PEMFC Power Source Used in Vehicular Applications
- A Novel Non-Linear Control for Three-Phase Five-Level Cascaded H-Bridge Inverter Based Shunt Active Power Filter
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- Enhancement of Power Quality in Wind Based Distributed Generation System Using Adaptive Vectorial Filter
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- Charging Coordination of Plug-In Electric Vehicle for Congestion Management in Distribution System
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- Multi-Objective based Optimal Generation Scheduling Considering Wind and Solar Energy Systems
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