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A Four-Antenna 802.11a Receiver integrated in 0.25 µm SiGe BiCMOS with Spatial Weighting

  • Michael Wickert EMAIL logo , Uwe Mayer , Ralf Eickhoff and Frank Ellinger
Published/Copyright: December 12, 2012
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Abstract

This paper presents the design and results of a four-antenna integrated receiver (RX) frontend in 0.25 µm SiGe BiCMOS. It performs antenna combining in the radio-frequency (RF) domain with IEEE 802.11a compliant signals. Therefore, the RF part of this integrated circuit (IC) includes four low noise amplifiers (LNAs), vector modulators (VMs) and a signal combiner. These circuits can weight the incoming C-band (5.6 GHz) signals in their I- and Q-components with an 8-bit resolution before superposition and downcoversion. The baseband (BB) part of the applied zero-IF architecture integrates an 8th order switched-capacitor (SC) filter for channel selection and variable gain amplifiers (VGAs) for automatic gain control (AGC). Together with digital control logic the power consumption amounts to 350 mW at an area requirement of 7.5 mm2.


Chair for Circuit Design and Network Theory, Technische Universität Dresden, 01062 Dresden, Germany

Received: 2012-07-30
Published Online: 2012-12-12
Published in Print: 2012-12-12

©[2012] by Walter de Gruyter Berlin Boston

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