A Fast-Locking Frequency Synthesizer for the Single-Chip CMOS UHF RFID Reader
-
Chunhua Wang
,
Guanchao Peng
Abstract
A fast-locking frequency synthesizer is designed for single-chip UHF RFID Reader. Different from the traditional UHF RFID frequency synthesizer, the technology of multi-modulus divider (MMD) is adopted here, which greatly reduces the design complexity. More importantly, two inverters and one toggle circuit are added to the output of the multi-modulus divider to improve the output load driving capability and the operation speed of the phase frequency detector (PFD), so as to reduce the locking time of the frequency synthesizer. Finally an improved divider by 2 is used at the output stage of the frequency, and the performance of the output waveform is improved. The simulation is made by Cadence in chartered 0.18 μm CMOS process. The simulation result shows that the output waveform is very good and the locking time is less than 10 μs. The phase noise of the output signal are approximately –104.8 dBc/Hz at 200 KHz and –124.6 dBc/Hz at 1MHz offset from 900MHz operating frequency, which is suitable for UHF RFID Reader. The frequency synthesizer dissipates 28.2mW with a 1.8V supply voltage.
Copyright © 2011 De Gruyter
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Articles in the same Issue
- Editorial
- Design of Compact Filter Based on Multilayered Left-Handed Transmission Line Using LTCC Technology
- A Metamaterial Inspired Compact Patch Antenna with Frequency Continuously Reconfigurable Performance for Cognitive Radio
- Nematic LCs Mixtures with High Birefringence in the Microwave Region
- A Fast-Locking Frequency Synthesizer for the Single-Chip CMOS UHF RFID Reader
- A Compact Analytical Design of Dual-Loop 18 GHz Frequency Synthesizer to Enhance Signal Reliability in Digital Millimeter Radio Link System
- Automatic Modulation Recognition of Mixed Multiple Source Signals
- A Current-Mode Common-Mode Feedback Circuit (CMFB) with Rail-to-Rail Operation
- Diversity and Multiplexing Tradeoff Analysis of Fractional Cooperative Networks
