Design and analysis of 2D 4 × 4 mesh NoC architecture with novel bufferless router for optical communication
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Ramanamma Parepalli
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Mohan Kumar Naik
Abstract
One common connectivity technology in large-scale tiled chip multiprocessors (TCMPs) is network-on-chip (NoC). There are two main types of NoC routers namely buffered and bufferless. Because of its hardware efficiency, lower energy usage, and simplified design, the latter presents a possible option. This paper suggests a new bufferless NoC router design for a 2D 4 × 4 mesh NoC architecture. Each of the four nearby peers (North, South, East, and West) and one processing element are linked to the routers that make up the suggested mesh network. The crossbar switch, input buffers, and output buffers are removed from the suggested router architecture. The combination of bufferless architecture, XY routing and dynamic prioritization establishes bufferless NoC as a robust and scalable solution for modern computing demands. Dynamic prioritization is a key feature in the proposed NoC architecture, which focuses on ensuring that data packets are processed efficiently and fairly, especially in scenarios with high traffic loads. Optical NoCs are based on optical interconnects and optical routers, and have significant bandwidth and power advantages. Our results indicate that the proposed bufferless router can lead to significant area (30.3 %) reduction over the standard BLESS. Simulation results demonstrate the effectiveness of the proposed architecture in terms of throughput, latency, and energy efficiency.
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Research ethics: Not applicable.
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Informed consent: Not applicable.
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Author contributions: The authors have accepted responsibility for the entire content of this manuscript and approved its submission.
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Use of Large Language Models, AI and Machine Learning Tools: Not applicable.
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Conflict of interest: The authors state no conflict of interest.
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Research funding: Not applicable.
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Data availability: Not applicable.
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