Bufferless NoC router design for optical networks-on-chip
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Ramanamma Parepalli
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Mohan Kumar Naik
Abstract
In large-scale tiled chip multiprocessors (TCMPs), network-on-chip (NoC) is a prevalent interconnect solution. The NoC router plays a crucial role in NoC architecture, and two primary types exist: buffered and bufferless. The latter offers a promising solution due to its streamlined design, reduced energy consumption, and hardware efficiency. This paper proposes a 2D 4 × 4 mesh NoC architecture with a novel bufferless NoC router design using XY routing algorithm. The proposed mesh network consists of routers and processing elements, with each router connected to its four adjacent peers (North, South, East, and West) and a single processing element. The proposed router design eliminates the input buffers, output buffers and crossbar switch. The novel bufferless NoC router architecture comprises of various functional blocks, including ejection and injection controllers and Data ranking based on port prioritization, and age incrementor which efficiently solves long critical path issues by dynamically changing the port priority and hence solves the deadlock issue. By leveraging efficient routing and prioritization mechanisms, the novel architecture facilitates the seamless flow of flits through the network. Optical NoCs are based on optical interconnects and optical routers, and have significant bandwidth and power advantages. Our results indicate that the proposed bufferless router can lead to significant area (30.3 %) reduction over the standard BLESS.
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Research ethics: Not applicable.
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Informed consent: Not applicable.
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Author contributions: The authors have accepted responsibility for the entire content of this manuscript and approved its submission.
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Use of Large Language Models, AI and Machine Learning Tools: None declared.
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Conflict of interest: The authors state no conflict of interest.
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Research funding: Not applicable.
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Data availability: Not applicable.
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