Optimizing multi-level ReRAM memory for low latency and low energy consumption

Shima Hosseinzadeh; Marius Klemm; Georg Fischer; Dietmar Fey

doi:10.1515/itit-2023-0022

Article

Optimizing multi-level ReRAM memory for low latency and low energy consumption

Shima Hosseinzadeh
Shima Hosseinzadeh received her first M.Sc. degree (2015) in Computer Science from Shahid Beheshti University, Tehran, Iran, and her second M.Sc. degree (2017) in Computer Architecture Engineering from (IAU) Science and Research Branch, Tehran, Iran. Currently, she is a Ph.D. Candidate at the Chair of Computer Architecture at Friedrich-Alexander-University Erlangen-Nuremberg (FAU), Erlangen, Germany. Her research interests include emerging non-volatile memories, especially ReRAM and FTJ, and their application in Processing-In-Memory.
, Marius Klemm
Marius Klemm received his B.Sc. and M.Sc. degree in Electrical Engineering with focus on microelectronics from the Friedrich-Alexander-Universität Erlangen-Nürnberg in 2020 and 2022. Since September 2022, he is working at Siemens Healthineers in Erlangen in a PCB design group as a signal integrity engineer for digital high-speed designs.
, Georg Fischer
Prof. Dr.-Ing. Georg Fischer studied electrical engineering at RWTH Aachen university from 1986 until 1992. From 1993 until 1996 he was a research assistant with university of Paderborn, responsible for the microwave and antenna lab there. In 1997 he obtained doctoral degree summa cum laude from university of Paderborn. From 1996 until 2008 he was working with Bell Labs research of Alcatel-Lucent researching cellular base stations and especially switch mode RF power amplifiers. In 2008 he received Professorship for electronics engineering at Friedrich-Alexander-Universität Erlangen-Nürnberg. His research interest is with analog-digital balance of electronic systems and analogue computation.
and Dietmar Fey
Prof. Dr.-Ing. Dietmar Fey Dietmar Fey is a Full Professor of Computer Science with Friedrich-Alexander-University Erlangen-Nürnberg (FAU). After his study in computer science at FAU he received his doctorate with a thesis in the field of Optical Computing in 1992 also at FAU. He was an Associate Professor from 2001 to 2009 for Computer Engineering with University Jena. Since 2009 he leads the Chair for Computer Architecture at FAU. He authored or co-authored more than 170 papers in proceedings and journals and published three books. Recently, he was involved in the establishing of a DFG priority program about memristive computing and in a research competition project awarded by the BMBF using memristive technology in deep neural networks.

Published/Copyright: May 3, 2023

Published by

Become an author with De Gruyter Brill

Submit Manuscript Author Information Explore this Subject

From the journal it - Information Technology Volume 65 Issue 1-2

Abstract

With decreasing die size and the ability to store multiple bits in a single cell, resistive random access memory (ReRAM) can be used to increase storage density, making it a promising technology for the next generation of memory. However, multi-level write operations suffer from impairments such as large latency, high energy consumption, and reliability issues. In this paper, we study different mechanisms affecting the “multi-level incremental step pulse with verify algorithm” (M-ISPVA) on a 1-transistor-1-resistor (1T1R) model in transient simulation at the component and the circuit level with focus on resistance control and energy consumption during the entire process of state transitions. By dividing the M-ISPVA into a triggering and a controlling period, we discovered the transistor to operate in the ohmic region during the triggering period as a voltage-controlled resistance and in the saturation region during the controlling period as a voltage-controlled current limiter. Controlling the gate voltage in the triggering period can move the triggering point to a desired write voltage and in the controlling period can increase or decrease resistance steps per pulse to attain a desired speed of resistance change. In addition, the major energy portion is consumed for reset operation during triggering and for set operation during the controlling period. To optimize write performance, extra precaution must be taken when defining resistance states with target read-out current and gate voltage with the focus on evenly balanced latencies between all transitions. A direct multi-level write operation shows 67.5 % latency and 62.5 % energy saving compared to indirect ones, but suffers from only unidirectional control, making it non-feasible. In case of a 4 k bit memory, the more reliable M-ISPVA faces almost 37 % higher latency and energy compared to the basic ISPVA.

Keywords: 1T1R; ISPVA; M-ISPVA; MLC; non-volatile memory; ReRAM; ternary memory model; write-verification

ACM CCS: hardware; integrated circuits; non-volatile memory; semiconductor memory

Corresponding author: Shima Hosseinzadeh, FAU Erlangen-Nürnberg, Department Computer Science 3, Martensstr. 3, 91058 Erlangen, Germany, E-mail: shima.hosseinzadeh@fau.de

About the authors

Shima Hosseinzadeh

Shima Hosseinzadeh received her first M.Sc. degree (2015) in Computer Science from Shahid Beheshti University, Tehran, Iran, and her second M.Sc. degree (2017) in Computer Architecture Engineering from (IAU) Science and Research Branch, Tehran, Iran. Currently, she is a Ph.D. Candidate at the Chair of Computer Architecture at Friedrich-Alexander-University Erlangen-Nuremberg (FAU), Erlangen, Germany. Her research interests include emerging non-volatile memories, especially ReRAM and FTJ, and their application in Processing-In-Memory.

Marius Klemm

Marius Klemm received his B.Sc. and M.Sc. degree in Electrical Engineering with focus on microelectronics from the Friedrich-Alexander-Universität Erlangen-Nürnberg in 2020 and 2022. Since September 2022, he is working at Siemens Healthineers in Erlangen in a PCB design group as a signal integrity engineer for digital high-speed designs.

Georg Fischer

Prof. Dr.-Ing. Georg Fischer studied electrical engineering at RWTH Aachen university from 1986 until 1992. From 1993 until 1996 he was a research assistant with university of Paderborn, responsible for the microwave and antenna lab there. In 1997 he obtained doctoral degree summa cum laude from university of Paderborn. From 1996 until 2008 he was working with Bell Labs research of Alcatel-Lucent researching cellular base stations and especially switch mode RF power amplifiers. In 2008 he received Professorship for electronics engineering at Friedrich-Alexander-Universität Erlangen-Nürnberg. His research interest is with analog-digital balance of electronic systems and analogue computation.

Dietmar Fey

Prof. Dr.-Ing. Dietmar Fey Dietmar Fey is a Full Professor of Computer Science with Friedrich-Alexander-University Erlangen-Nürnberg (FAU). After his study in computer science at FAU he received his doctorate with a thesis in the field of Optical Computing in 1992 also at FAU. He was an Associate Professor from 2001 to 2009 for Computer Engineering with University Jena. Since 2009 he leads the Chair for Computer Architecture at FAU. He authored or co-authored more than 170 papers in proceedings and journals and published three books. Recently, he was involved in the establishing of a DFG priority program about memristive computing and in a research competition project awarded by the BMBF using memristive technology in deep neural networks.

Author contribution: All the authors have accepted responsibility for the entire content of this submitted manuscript and approved submission.
Research funding: None declared.
Conflict of interest statement: The authors declare no conflicts of interest regarding this article.

References

[1] C. Xu, D. Niu, N. Muralimanohar, et al.., “Overcoming the challenges of crossbar resistive memory architectures,” in HPCA, 2015, pp. 476–488.10.1109/HPCA.2015.7056056Search in Google Scholar

[2] M. A. Lastras-Montaño, A. Ghofrani, and K. Cheng, “A low-power hybrid reconfigurable architecture for resistive random-access memories,” in HPCA, 2016, pp. 102–113.10.1109/HPCA.2016.7446057Search in Google Scholar

[3] H. S. P. Wong, H. Y. Lee, S. Yu, et al.., “Metal–oxide rram,” Proc. IEEE, vol. 100, pp. 1951–1970, 2012. https://doi.org/10.1109/jproc.2012.2190369.Search in Google Scholar

[4] A. A. El-Slehdar, A. H. Fouad, and A. G. Radwan, “Memristor-based balanced ternary adder,” in ICM, 2013, pp. 1–4.10.1109/ICM.2013.6735002Search in Google Scholar

[5] S. Yu, X. Guan, and H. S. P. Wong, “On the switching parameter variation of metal oxide rram—part ii: model corroboration and device design strategy,” IEEE Trans. Electron. Dev., vol. 59, pp. 1183–1188, 2012. https://doi.org/10.1109/ted.2012.2184544.Search in Google Scholar

[6] A. Grossi, E. Nowak, C. Zambelli, et al.., “Fundamental variability limits of filament-based rram,” in 2016 IEEE International Electron Devices Meeting (IEDM), 2016, pp. 4–7.10.1109/IEDM.2016.7838348Search in Google Scholar

[7] E. Pérez, C. Zambelli, M. K. Mahadevaiah, P. Olivo, and C. Wenger, “Toward reliable multi-level operation in rram arrays: improving post-algorithm stability and assessing endurance/data retention,” IEEE J. Electron Devices Soc., vol. 7, pp. 740–747, 2019. https://doi.org/10.1109/jeds.2019.2931769.Search in Google Scholar

[8] Y. Y. Chen, L. Goux, S. Clima, et al.., “Endurance/retention trade-off on HfO2/Metal cap 1t1r bipolar rram,” IEEE Trans. Electron Devices, vol. 60, pp. 1114–1121, 2013. https://doi.org/10.1109/ted.2013.2241064.Search in Google Scholar

[9] C. Y. Lin, C. Y. Wu, T. C. Lee, et al.., “Effect of top electrode material on resistive switching properties of ZrO2 film memory devices,” IEEE Electron Device Lett., vol. 28, pp. 366–368, 2007. https://doi.org/10.1109/led.2007.894652.Search in Google Scholar

[10] T. Cabout, J. Buckley, C. Cagli, et al.., “Role of ti and pt electrodes on resistance switching variability of hfo2-based resistive random access memory,” Thin Solid Films, vol. 533, pp. 19–23, 2013. https://doi.org/10.1016/j.tsf.2012.11.050.Search in Google Scholar

[11] J. Park, M. Jo, S. Jung, et al.., “New set/reset scheme for excellent uniformity in bipolar resistive memory,” IEEE Electron Device Lett., vol. 32, pp. 228–230, 2011. https://doi.org/10.1109/led.2010.2094599.Search in Google Scholar

[12] A. Grossi, C. Zambelli, P. Olivo, et al.., “Electrical characterization and modeling of pulse-based forming techniques in rram arrays,” Solid-State Electron., vol. 115, pp. 17–25, 2016. https://doi.org/10.1016/j.sse.2015.10.003.Search in Google Scholar

[13] K. Higuchi, T. Iwasaki, and K. Takeuchi, “Investigation of verify-programming methods to achieve 10 million cycles for 50nm hfo2 reram,” in IMW, 2012, pp. 1–4.10.1109/IMW.2012.6213665Search in Google Scholar

[14] Y. L. Song, Y. Meng, X. Y. Xue, et al.., “Reliability significant improvement of resistive switching memory by dynamic self-adaptive write method,” in VLSIT, 2013, pp. T102–T103.Search in Google Scholar

[15] E. Pérez, A. Grossi, C. Zambelli, P. Olivo, and C. Wenger, “Impact of the incremental programming algorithm on the filament conduction in hfo2-based rram arrays,” IEEE J. Electron Devices Soc., vol. 5, pp. 64–68, 2017. https://doi.org/10.1109/jeds.2016.2618425.Search in Google Scholar

[16] E. Pérez, A. Grossi, C. Zambelli, M. K. Mahadevaiah, P. Olivo, and C. Wenger, “Temperature impact and programming algorithm for rram based memories,” in IMWS-AMP, 2018, pp. 1–3.10.1109/IMWS-AMP.2018.8457132Search in Google Scholar

[17] D. Fey, “Using the multi-bit feature of memristors for register files in signed-digit arithmetic units,” Semicond. Sci. Technol., vol. 29, p. 104008, 2014. https://doi.org/10.1088/0268-1242/29/10/104008.Search in Google Scholar

[18] D. Fey, M. Reichenbach, C. Söll, M. Biglari, J. Röber, and R. Weigel, “Using memristor technology for multi-value registers in signed-digit arithmetic circuits,” in MEMSYS, 2016, pp. 442–454.10.1145/2989081.2989124Search in Google Scholar

[19] W. Kim, A. Chattopadhyay, A. Siemon, E. Linn, R. Waser, and V. Rana, “Multistate memristive tantalum oxide devices for ternary arithmetic,” Sci. Rep., vol. 6, p. 36652, 2016. https://doi.org/10.1038/srep36652.Search in Google Scholar PubMed PubMed Central

[20] S. Hosseinzadeh, M. Biglary, and D. Fey, “Tremo: a model for ternary reram-based memories with adjustable write-verification capabilities,” in DSD, 2020, pp. 44–48.10.1109/DSD51259.2020.00019Search in Google Scholar

[21] S. Hosseinzadeh, M. Biglari, and D. Fey, “Tremo+: modeling ternary and binary reram-based memories with flexible write-verification mechanisms,” Front. Nanotechnol., vol. 3, p. 765947, 2021. https://doi.org/10.3389/fnano.2021.765947.Search in Google Scholar

[22] C. Xu, D. Niu, N. Muralimanohar, N. P. Jouppi, and Y. Xie, “Understanding the trade-offs in multi-level cell reram memory design,” in DAC, 2013, pp. 1–6.10.1145/2463209.2488867Search in Google Scholar

[23] K. Kinoshita, K. Tsunoda, Y. Sato, et al.., “Reduction of reset current in nio-reram brought about by ideal current limiter,” in NVSMW, 2007, pp. 66–67.10.1109/NVSMW.2007.4290583Search in Google Scholar

[24] A. Siemon, S. Menzel, R. Waser, and E. Linn, “A complementary resistive switch-based crossbar array adder,” IEEE CAS, vol. 5, pp. 64–74, 2015.10.1109/JETCAS.2015.2398217Search in Google Scholar

[25] Z. Jiang, Y. Wu, S. Yu, et al.., “A compact model for metal–oxide resistive random access memory with experiment verification,” IEEE Trans. Electron Devices, vol. 63, pp. 1884–1892, 2016. https://doi.org/10.1109/ted.2016.2545412.Search in Google Scholar

[26] P. Chi, S. Li, C. Xu, et al.., “Prime: a novel processing-in-memory architecture for neural network computation in reram-based main memory,” SIGARCH Comput. Archit. News, vol. 44, pp. 27–39, 2016. https://doi.org/10.1145/3007787.3001140.Search in Google Scholar

[27] S. H. Pugsley, J. Jestes, H. Zhang, et al.., “Ndc: analyzing the impact of 3d-stacked memory+logic devices on mapreduce workloads,” in 2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2014, pp. 190–200.10.1109/ISPASS.2014.6844483Search in Google Scholar

[28] E. P. B. Quesada, M. K. Mahadevaiah, T. Rizzi, et al.., “Experimental assessment of multilevel rram-based vector-matrix multiplication operations for in-memory computing,” IEEE Trans. Electron Devices, vol. 70, pp. 2009–2014, 2023. https://doi.org/10.1109/ted.2023.3244509.Search in Google Scholar

[29] J. J. Yang, M. D. Pickett, X. Li, D. A. A. Ohlberg, D. R. Stewart, and R. S. Williams, “Memristive switching mechanism for metal/oxide/metal nanodevices,” Nat. Nanotechnol., vol. 3, pp. 429–433, 2008. https://doi.org/10.1038/nnano.2008.160.Search in Google Scholar PubMed

[30] X. Dong, C. Xu, Y. Xie, and N. P. Jouppi, “Nvsim: a circuit-level performance, energy, and area model for emerging nonvolatile memory,” IEEE CEDA, vol. 31, pp. 994–1007, 2012.10.1109/TCAD.2012.2185930Search in Google Scholar

[31] M. Biglari, T. Lieske, and D. Fey, “High-endurance bipolar reram-based non-volatile flip-flops with run-time tunable resistive states,” in NANOARCH, 2018, pp. 19–24.10.1145/3232195.3232217Search in Google Scholar

[32] J. Reuben, D. Fey, and C. Wenger, “A modeling methodology for resistive ram based on stanford-pku model with extended multilevel capability,” IEEE Trans. Nanotechnol., vol. 18, pp. 647–656, 2019. https://doi.org/10.1109/tnano.2019.2922838.Search in Google Scholar

[33] J. Sandrini and Y. Leblebici, “Fabrication, characterization and integration of resistive random access memories,” Ph.D. thesis, École Polytechnique Fédérale De Lausanne, 2017.Search in Google Scholar

[34] K. Fleck, U. Böttger, R. Waser, N. Aslam, S. Hoffmann-Eifert, S. Menzel., “Energy dissipation during pulsed switching of strontium-titanate based resistive switching memory devices,” in 2016 46th European Solid-State Device Research Conference (ESSDERC), 2016, pp. 160–163.10.1109/ESSDERC.2016.7599611Search in Google Scholar

[35] A. Hardtdegen, C. La Torre, F. Cuppers, S. Menzel, R. Waser, and S. Hoffmann-Eifert, “Improved switching stability and the effect of an internal series resistor in hfo2/tiox bilayer reram cells,” IEEE Trans. Electron Devices, vol. 65, pp. 3229–3236, 2018. https://doi.org/10.1109/ted.2018.2849872.Search in Google Scholar

[36] C. Felix, S. Menzel, C. Bengel, et al.., “Exploiting the switching dynamics of hfo2-based reram devices for reliable analog memristive behavior,” APL Mater., vol. 7, p. 091105, 2019. https://doi.org/10.1063/1.5108654.Search in Google Scholar

[37] C. Bengel, K. Zhang, J. Mohr, et al.., “Tailor-made synaptic dynamics based on memristive devices,” Front. Electron. Mater., vol. 3, p. 1061269, 2023. https://doi.org/10.3389/femat.2023.1061269.Search in Google Scholar

Received: 2023-04-09

Accepted: 2023-04-09

Published Online: 2023-05-03

Published in Print: 2023-05-25

You are currently not able to access this content.

Articles in the same Issue

https://doi.org/10.1515/itit-2023-0022

Keywords for this article

1T1R; ISPVA; M-ISPVA; MLC; non-volatile memory; ReRAM; ternary memory model; write-verification